Computer Architecture I: Digital Design

1
Computer Architecture I Digital Design Dr.
Robert D. Kent
CPU Registers Register Transfer and
Microoperations
2
Review

• We have introduced registers previously.
• Registers are constructed using flip-flops and
  combinational circuits that enable one to
• Refresh volatile data
• Load (Store) data
• Clear storages (change all bits to 0)
• Increment (and decrement) storages binarily
• Complement storages
• Select individual storage bits

3
Considering the next problem in design

• When designing complex computer systems it is
  important to understand that we start from very
  small components for which the operational
  characteristics are extremely well defined.
• We then applied Bottom-Up Hierarchical design to
  identify commonly used networks (ie. circuits) of
  smaller components, from SSI to MSI. At this
  stage the descriptive language (and symbols)
  changes.
• SSI as OR transforms to MSI as ADD
• Now as we consider MSI to LSI, and also
  MSI-to-MSI networks, such as the CPU, our
  language must again change to fit the nature of
  design.

4
Goals

• The Mano model of the CPU Registers
• Registers
• Bus network
• Register and Memory Transfer
• A language for describing hardware function
• A language for denoting implementation
• A language that bridges LSI/MSI
• Microoperations Application examples
• Arithmetic
• Logic
• Shift

5
The Mano model of the CPU Registers

• CPU registers used in the textbook (Mano)
• PC Program counter
• IR Instruction register
• AR Address register
• DR Data register (also called MBR
  Memory Buffer Reg.)
• AC Accumulator
• INR Input buffer register
• OUTR Output buffer register
• SCR Sequence counter register

6
The Mano model of the CPU Registers

• CPU registers are organized on an internal bus
  network
• Accessible using a multiplexer
• Registers are selected according to selection
  inputs

PC
0 1 2 3 4 5 6 7
Typically, the number of registers is chosen as a
power of 2. This simplifies the choice of MUX
and the bus architecture.
AR
DR
IR
Data OUT
AC
INR
OUTR
Demultiplexers are used to input data to
registers.
SCR
Register Address
7
Reminder!

• CPU register operations should be among the
  fastest of hardware operations
• All instructions are executed in CPU
• Few registers implies more complex circuits may
  be employed to control data processing and
  workflow
• We need a language that allows us to describe
  what we want to happen (operationally) in a
  circuit, while achieving an actual working
  hardware system to accomplish our requirements
• We must also understand the complexities or
  behaviours of the circuits, such as performance
  based on numbers of logic stages, degrees of
  parallel versus serial capacity, response and
  other factors

8
Register Transfer

• First, review what we have learned so far about
  registers
• We combined the basic building blocks of bit
  storage units (ie. flip-flops) to form storage
  units of multiple bits called registers
• We combined registers with more complicated
  circuitry to perform various operations
• Some serial operations
• Some parallel operations
• We combined several operations together into even
  more complicated circuits
• The choice of operation is determined by Selector
  inputs using either Multi-Input Control, or
  Multiplexer Selection.

9
Register Parallel Load

• Register flip-flops should refresh or load
  simultaneously.

Single Operation
10
Register Count/Load/Clear

• Combine counting (INC), loading (L) and
  synchronous clearing (C). Can also add
  Complementation (JK1).

C L Inc I0 I1 Clk
Multi-Input Selection Multiple Operations
A0 A1
Carry Out
(See Fig. 2-11 in Mano)
11
Register Shift/Load/Refresh

• Bi-directional shifting can be combined with
  parallel load and refresh operations. This
  requires use of multiplexers.

Function Table Function Table Function Table Function Table
Mode Control Mode Control
S1 S0 Register Operation
0 0 Refresh no change
0 1 Shift right
1 0 Shift left
1 1 Parallel load
12
Register Shift/Load/Refresh

• Bi-directional shifting can be combined with
  parallel load and refresh operations.

Multiplexer Selection Multiple Operations
S0 S1 Serial in I0 Serial in I1 Clk
S0 S1 0 4x1 1 MUX 2 3
A0 A1
S0 S1 0 4x1 1 MUX 2 3
(See Fig. 2-9 in Mano)
13
Registers Multi-Operation Control

• Selection of specific operations (or even groups
  of operations) can be accomplished in several
  ways.
• Single selection
• Dedicated circuits
• Multi-selection
• Multiplexed selection
• Multi-input selection
• Hybrid selection, combining both multiplexers and
  multi-inputs
• Unfortunately we do not have time to discuss the
  fullest implications of this important topic.
• Interested students should read advanced chapters
  of Mano (Chapter 6 and higher).

14
Register Transfer

• The internal hardware organization of a digital
  computer is best defined by specifying
• The set of registers it contains and their
  function
• The sequence of microoperations performed on the
  binary data stored in the registers
• The control that initiates the sequence of
  microoperations

15
Register Transfer

• Notations and conventions
• Copy (ie. transfer) all data from one register
  (R1) to another (R2).
• May be parallel or serial, but we do not need to
  ask

R2 R1 Use for print convenience
16
Register Transfer

• Notations and conventions
• If we intend to copy only a portion of data it is
  important to specify precisely where the data is
  located within the storage.

17
Register Transfer

• Notations and conventions
• Conditional transfer
• If ( P 1) then ( R2 R1 )
• This can be rewritten in the compact form
• P R2 R1
• Finally, we can combine several operations in
  parallel
• T R2 R1 , R4 R3

Parallel operations in hardware must be carefully
checked for consistency to ensure they are
sensible (achievable) and not just nonsense.
18
Memory

• RAM storages are typically constructed as a
  single unit called a byte.
• Although the standard storage unit for data is
  8-bits (flip-flops), additional bits are used for
  a variety of purposes
• especially error checking (Hamming Codes)
• Each byte is located at a fixed address
• Starts at address 0 and increases contiguously up
  to a maximum address, usually a power of 2
• Review lecture on multiplexers as address
  selectors enabling data transfer from selected
  bytes
• The byte is called the smallest unit of
  addressable memory.

19
Memory Transfer

• We reserve the letter M to denote volatile memory
  (ie. RAM)
• Data in memory needs to be referenced by its
  location, or address
• Maddress refers to the data stored at
  address
• M04C8 refers to the data stored at
  address 04C8
• MAR refers to the data stored at the
  address which is itself stored
  in the register AR (address register)

Read operation DR MAR Write operation
MAR DR
20
Microoperations
Micro-operations are considered fundamental, or
primitive (usually atomic) operations carried out
in the CPU or elsewhere.

1. Register transfer microoperations transfer binary
   data from one register to another register.
2. Arithmetic microoperations perform arithmetic
   operations on numeric data stored in registers.
3. Logic microoperations perform bit manipulation
   operations on non-numeric data stored in
   registers.
4. Shift microoperations perform shift operations on
   data stored in registers.

21
Arithmetic Microoperations

• Arithmetic microoperations perform arithmetic
  operations on numeric data stored in registers.

Arithmetic Microoperations Arithmetic Microoperations
Symbolic Descriptive
R3 R1 R2 Contents of R1 plus R2 transferred to R3
R3 R1 R2 Contents of R1 minus R2 transferred to R3
R1 R1 1s complement the contents of R1
R2 R2 1 2s complement the contents of R2 (negate)
R3 R1 R2 1 R1 plus 2s complement of R2 (subtraction)
R1 R1 1 Increment the contents of R1 by one
R2 R2 1 Decrement the contents of R2 by one
22
Arithmetic Microoperations

• Arithmetic microoperations perform arithmetic
  operations on numeric data stored in registers.

Arithmetic Microoperations Arithmetic Microoperations
Symbolic Descriptive
R3 R1 R2 Contents of R1 plus R2 transferred to R3
R3 R1 R2 Contents of R1 minus R2 transferred to R3
R1 R1 1s complement the contents of R1
R2 R2 1 2s complement the contents of R2 (negate)
R3 R1 R2 1 R1 plus 2s complement of R2 (subtraction)
R1 R1 1 Increment the contents of R1 by one
R2 R2 1 Decrement the contents of R2 by one
23
Arithmetic Microoperations

• Arithmetic microoperations perform arithmetic
  operations on numeric data stored in registers.

Arithmetic Microoperations Arithmetic Microoperations
Symbolic Descriptive
R3 R1 R2 Contents of R1 plus R2 transferred to R3
R3 R1 R2 Contents of R1 minus R2 transferred to R3
R1 R1 1s complement the contents of R1
R2 R2 1 2s complement the contents of R2 (negate)
R3 R1 R2 1 R1 plus 2s complement of R2 (subtraction)
R1 R1 1 Increment the contents of R1 by one
R2 R2 1 Decrement the contents of R2 by one
24
Arithmetic Microoperations

• Arithmetic microoperations perform arithmetic
  operations on numeric data stored in registers.

Arithmetic Microoperations Arithmetic Microoperations
Symbolic Descriptive
R3 R1 R2 Contents of R1 plus R2 transferred to R3
R3 R1 R2 Contents of R1 minus R2 transferred to R3
R1 R1 1s complement the contents of R1
R2 R2 1 2s complement the contents of R2 (negate)
R3 R1 R2 1 R1 plus 2s complement of R2 (subtraction)
R1 R1 1 Increment the contents of R1 by one
R2 R2 1 Decrement the contents of R2 by one
25
Arithmetic Microoperations

• Arithmetic microoperations perform arithmetic
  operations on numeric data stored in registers.

Arithmetic Microoperations Arithmetic Microoperations
Symbolic Descriptive
R3 R1 R2 Contents of R1 plus R2 transferred to R3
R3 R1 R2 Contents of R1 minus R2 transferred to R3
R1 R1 1s complement the contents of R1
R2 R2 1 2s complement the contents of R2 (negate)
R3 R1 R2 1 R1 plus 2s complement of R2 (subtraction)
R1 R1 1 Increment the contents of R1 by one
R2 R2 1 Decrement the contents of R2 by one
26
Arithmetic Microoperations

• Multiple operations can be multiplexed together
• Adder-Subtractor
• Shift Left/Right
• Logical
• Arithmetic
• Increment/Decrement
• Load
• And so on .

27
Arithmetic Microoperations

• Arithmetic microoperations perform arithmetic
  operations on numeric data stored in registers.

Arithmetic Circuit Function Selection Table Arithmetic Circuit Function Selection Table Arithmetic Circuit Function Selection Table Arithmetic Circuit Function Selection Table Arithmetic Circuit Function Selection Table Arithmetic Circuit Function Selection Table
Select Select Select Input Output
S1 S2 Cin Y D A Y Cin Microoperation
0 0 0 B D A B Add
0 0 1 B D A B 1 Add with carry
0 1 0 B D A B Subtract with borrow
0 1 1 B D A B 1 Subtract
1 0 0 0 D A Transfer A
1 0 1 0 D A 1 Increment A
1 1 0 1 D A - 1 Decrement A
1 1 1 1 D A Transfer A
28
Arithmetic Microoperations

• Arithmetic microoperations perform arithmetic
  operations on numeric data stored in registers.

Arithmetic Circuit Function Selection Table Arithmetic Circuit Function Selection Table Arithmetic Circuit Function Selection Table Arithmetic Circuit Function Selection Table Arithmetic Circuit Function Selection Table Arithmetic Circuit Function Selection Table
Select Select Select Input Output
S1 S2 Cin Y D A Y Cin Microoperation
0 0 0 B D A B Add
0 0 1 B D A B 1 Add with carry
0 1 0 B D A B Subtract with borrow
0 1 1 B D A B 1 Subtract
1 0 0 0 D A Transfer A
1 0 1 0 D A 1 Increment A
1 1 0 1 D A - 1 Decrement A
1 1 1 1 D A Transfer A
29
Arithmetic Microoperations
Note that S1 and S2 are multiplexer selector
inputs, whereas Cin is a separated input.

• Arithmetic microoperations perform arithmetic
  operations on numeric data stored in registers.

Arithmetic Circuit Function Selection Table Arithmetic Circuit Function Selection Table Arithmetic Circuit Function Selection Table Arithmetic Circuit Function Selection Table Arithmetic Circuit Function Selection Table Arithmetic Circuit Function Selection Table
Select Select Select Input Output
S1 S2 Cin Y D A Y Cin Microoperation
0 0 0 B D A B Add
0 0 1 B D A B 1 Add with carry
0 1 0 B D A B Subtract with borrow
0 1 1 B D A B 1 Subtract
1 0 0 0 D A Transfer A
1 0 1 0 D A 1 Increment A
1 1 0 1 D A - 1 Decrement A
1 1 1 1 D A Transfer A
30
Logic Microoperations

• Logic microoperations perform bit manipulation
  operations on non-numeric data stored in
  registers.

31
Logic Microoperations

• Consider all possible bit operations involving 2
  inputs

32
Logic Microoperations

• By labeling each possible operation we derive the
  following table.

Sixteen Fundamental Logic Microoperations Sixteen Fundamental Logic Microoperations Sixteen Fundamental Logic Microoperations Sixteen Fundamental Logic Microoperations Sixteen Fundamental Logic Microoperations Sixteen Fundamental Logic Microoperations
MicroOp Name MicroOp Name
0 F 0 Clear 8 F AB NOR (AB)
1 F AB AND 9 F ABAB eXclusive NOR
2 F AB Selective clear A 10 F B Complement B
3 F A Transfer A 11 F AB Selective set A
4 F AB Selective clear B 12 F A Complement A
5 F B Transfer B 13 F AB Selective set B
6 F ABAB eXclusive OR 14 F AB NAND (AB)
7 F AB OR 15 F 1 Set
33
Logic Microoperations

• Refer to Mano
• Multiplexed Logic Circuit (Figure 4.10)
• Applications discussion, pages 11-113

34
Shift Microoperations

• Shift microoperations perform shift operations on
  data stored in registers.

Shift Microoperations Shift Microoperations
Symbolic Descriptive
R shl R Shift-left logical register R
R shr R Shift-right logical register R
R cil R Circular shift-left register R
R cir R Circular shift-right register R
R ashl R Shift-left arithmetic register R
R ashr R Shift-right arithmetic register R
35
Shift Microoperations

• Shift microoperations perform shift operations on
  data stored in registers.

Shift Microoperations Shift Microoperations
Symbolic Descriptive
R shl R Shift-left logical register R
R shr R Shift-right logical register R
R cil R Circular shift-left register R
R cir R Circular shift-right register R
R ashl R Shift-left arithmetic register R
R ashr R Shift-right arithmetic register R
36
Shift Microoperations

• Shift microoperations perform shift operations on
  data stored in registers.

Shift Microoperations Shift Microoperations
Symbolic Descriptive
R shl R Shift-left logical register R
R shr R Shift-right logical register R
R cil R Circular shift-left register R
R cir R Circular shift-right register R
R ashl R Shift-left arithmetic register R
R ashr R Shift-right arithmetic register R
37
Shift Microoperations

• Shift microoperations perform shift operations on
  data stored in registers.

Shift Microoperations Shift Microoperations
Symbolic Descriptive
R shl R Shift-left logical register R
R shr R Shift-right logical register R
R cil R Circular shift-left register R
R cir R Circular shift-right register R
R ashl R Shift-left arithmetic register R
R ashr R Shift-right arithmetic register R
38
Shift Microoperations

• Shift microoperations perform shift operations on
  data stored in registers.

Shift Microoperations Shift Microoperations
Symbolic Descriptive
R shl R Shift-left logical register R
R shr R Shift-right logical register R
R cil R Circular shift-left register R
R cir R Circular shift-right register R
R ashl R Shift-left arithmetic register R
R ashr R Shift-right arithmetic register R
39
Shift Microoperations

• Assume registers have L bits, each represented by
  a D flip-flop.

F(i) F(i) i0?0F(i-1) iL-1?0F(i1) F(
(Li-1)L ) F( (Li1)L ) i0?0F(i-1) iL-1?F(L)
F(i1)
D Q FF(i)
F(i)
REGISTER
SELECTION CONTROL
40
Shift Microoperations

• Assume registers have L bits, each represented by
  a D flip-flop.

F(i) F(i) i0?0F(i-1) iL-1?0F(i1) F(
(Li-1)L ) F( (Li1)L ) i0?0F(i-1) iL-1?F(L)
F(i1)
D Q FF(i)
F(i)
41
Arithmetic Logic Shift Unit

• Mano discusses a multi-stage circuit
• Arithmetic stage
• Logic stage
• Multiplexed selection of operation
• Read
• Accompanying text

42
More Advanced Microoperations

• The following topics are discussed later in Mano
  (3d Edition Chapters 6-10) and will be studied in
  the course 60-460 (Advanced Architecture).
• Integer Multiplication Division
• Floating Point Architectures
• FP Register design
• FP Microoperations
• Input/Output Architectures
• The discussion in the lecture is oral and
  conceptual. There are no points discussed that
  are important for examinations this is optional
  material that will not be tested.

43
Three-State Buffers

• An important device called a 3-state bus buffer
  has been developed.
• Basically a capacitor with an impedance trigger
• Capacitors can hold a charge (equivalently, a
  voltage level) for a long time until an event
  triggers the release of the charge (equivalently,
  allows a voltage level to pass onto a connecting
  wire).

Impedance refers to a property of electrical
circuits, where current does not flow between
connected wires or gates unless the impedances
match in the connected sub-systems.

• Thus, if C0, no signal flows from A to Y. Y is
  therefore not defined.
• However, if C1, impedances are matched and
  signal flows from A to Y. The value at Y is
  then A.

44
Three-State Buffers

• 3-state bus buffers are often used at the outputs
  of storage flip-flops.
• Essentially, the buffer unit holds the value
  stored in the FF.
• Holding is useful for synchronizing enabling of
  parallel circuits
• The buffer unit can be used along with a Decoder
  unit as a replacement for an address multiplexer.
• This is an alternative approach.

45
Three-State Buffers

• 3-state bus buffers are often used at the outputs
  of storage flip-flops.
• Essentially, the buffer unit holds the value
  stored in the FF.
• Holding is useful for synchronizing enabling of
  parallel circuits
• The buffer unit can be used along with a Decoder
  unit as a replacement for an address multiplexer.
• This is an alternative approach.

0 1 1
46
Summary

• We introduced Manos basic CPU architecture
• Registers
• Bus
• We discussed Register and Memory Transfer and
  introduced a language suitable for description
  and design
• We presented several example applications of
  RTL/MTL for Microoperations
• Arithmetic
• Logic
• Shift
• We discussed briefly more advanced applications