Synthesis%20of%20False%20Target%20Radar%20Images%20Using%20a%20Reconfigurable%20Computer

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Synthesis of False Target Radar ImagesUsing a
Reconfigurable Computer

• Dr. Douglas J. Fouts
• LT Kendrick R. Macklin
• Daniel P. Zulaica
• Department of Electrical
• and Computer Engineering
• U.S. Naval Postgraduate School
• Monterey, California

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Outline
Synthesis of False Target Radar Images Using a
Reconfigurable Computer

1. High resolution imaging inverse synthetic
   aperture radar (ISAR).
2. Digital synthesis of realistic false target
   images.
3. The SRC-6E reconfigurable computer.
4. Synthesis of false target images on the SRC-6E.
5. Testing results.
6. Conclusions

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Synthesis of False Target Radar Images Using a
Reconfigurable Computer
The USS Crockett, a typical target for a
potential adversary.
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Synthesis of False Target Radar Images Using a
Reconfigurable Computer
Target appearance on the screen of a typical
surface search and navigation radar.
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Synthesis of False Target Radar Images Using a
Reconfigurable Computer
Appearance of USS Crockett on U.S. Navy
AN/APS-137 imaging Inverse Synthetic Aperture
Radar (ISAR).
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Synthesis of False Target Radar Images Using a
Reconfigurable Computer
Block diagram of electronic warfare system with
false target image synthesis capability.
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Synthesis of False Target Radar Images Using a
Reconfigurable Computer
Dividing a target into range bins.
Range Bins
Interrogating Radar Signal
Reflected Radar Signal
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Synthesis of False Target Radar Images Using a
Reconfigurable Computer
Block diagram of digital image synthesis hardware.
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Synthesis of False Target Radar Images Using a
Reconfigurable Computer
To synthesize a false target image, the math must
be done very fast.
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Synthesis of False Target Radar Images Using a
Reconfigurable Computer
RTL diagram of Range Bin Processor
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The SRC-6E Reconfigurable Computer
Synthesis of False Target Radar Images Using a
Reconfigurable Computer

• LINUX cluster of two PCs
• Each PC has
• Two 1000 MHz Intel XEON processors
• Common memory
• Snap port to Multi Adaptive Processor (MAP)
• Each MAP has
• Two user-programmable Xilinx Virtex-II FPGAs (6 M
  gates each)
• One Xilinx Virtex-II Control FPGA (not user
  programmable)
• On-board memory
• Snap port to PC
• Two 96-bit wide chain ports to other MAP
• Programs written in C or Fortran.
• User identifies which part(s) of program are
  converted to FPGA circuitry for (hopefully)
  increased execution speed
• FPGA code can also be written in VHDL OR Verilog
• FPGA can also be programmed schematically or with
  IP cores

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SRC-6E Architecture (half)
Synthesis of False Target Radar Images Using a
Reconfigurable Computer
µP
Board

MAP
Intel µP
Intel µP
315/195 MB/s (peak)
Controller
L2
L2
6x 800 MB/s
MIOC
On-Board Memory (24 MB)
6x 800 MB/s
SNAP
PCI
Common Memory
Chain Port To/From Other MAP 800 MB/s
Chain Port To/From Other MAP 800 MB/s
FPGA
FPGA
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MAP Software Development
Synthesis of False Target Radar Images Using a
Reconfigurable Computer

• Code for FPGAs is isolated in external function
• SRC compiler translates C source code into FPGA
  programming file.
• MAP can also be programmed with Verilog, VHDL, IP
  cores, or schematically
• FPGA circuitry deeply pipelined with 100 MHz
  clock (10 ns period)
• Large pipeline fill time (large latency)
• Calls are inserted in the main program to
• Initialize the MAP
• Transfer input data from common memory to
  on-board memory
• Call the external function
• Transfer output data from on-board memory to
  common memory
• Release the MAP (optional)

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Synthesis of False Target Radar Images Using a
Reconfigurable Computer
Programming Steps Used in This Research

• Describe range bin processor using VHDL in the
  Aldec Active-HDL 5.2 environment
• Code the individual logic blocks
• Combine to build a single range bin processor
• Instance the range bin processor the required
  number of times
• Test code using Aldec Active-HDL simulator
• Create support and interface files for SRC-6E
• Create main part of program in C for execution
  on PCs in SRC-6E
• Compile and link

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Synthesis of False Target Radar Images Using a
Reconfigurable Computer
Benchmarks

• VHDL macro on the SRC-6E MAP
• C program on the SRC-6E
• 1 GHz Xeon P3
• 1.5 Gigabytes of RAM
• Linux OS
• C program on Pentium 4 system
• 3 GHz P4
• 2 Gigabytes of RAM
• Windows XP Professional OS

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Synthesis of False Target Radar Images Using a
Reconfigurable Computer
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Synthesis of False Target Radar Images Using a
Reconfigurable Computer
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Synthesis of False Target Radar Images Using a
Reconfigurable Computer
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Synthesis of False Target Radar Images Using a
Reconfigurable Computer
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Synthesis of False Target Radar Images Using a
Reconfigurable Computer
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Synthesis of False Target Radar Images Using a
Reconfigurable Computer
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Synthesis of False Target Radar Images Using a
Reconfigurable Computer
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Conclusions
Synthesis of False Target Radar Images Using a
Reconfigurable Computer

1. The SRC-6E compiler allows C programmers to
   utilize the MAP without having to become circuit
   designers.
2. Porting code to the MAP requires basic knowledge
   of the hardware.
3. Programming an SRC-6E requires less time and
   effort than developing FPGA designs using COTS
   FPGA development systems.
4. Overall performance of SRC-6E can be limited by
   transfer time between common memory and on-board
   memory.
5. Use of large data sets amortizes MAP overhead and
   pipeline latency across many calculations.
6. Applications performing a large number of
   calculations on each data set derive the largest
   performance boost from using the MAP.