Digital Decode

1
Digital Decode Correction Logic

• Preliminary design review
• PAYAL DAVE

2
Outline

• Introduction
• Why Digital Decode Error correction logic
  requires
• Main Block diagram
• Individual block explanation
• Sims result
• Conclusion

3
A7
B7
A6
B6
A5
B5
D7
D6
D5
4
Need for Digital Decode Error Correction

• To eliminate the redundancy of ½ bit in each
  stage
• Digital correction takes raw output data of the
  ADC as input and outputs the digital
  representation.
• Error correction logic circuitry takes 14 bit
  input from ADC stages and eliminated the
  redundancy of ½ bit in each stage and gives 8 bit
  digital output.
• Digital circuits are fast and take low power.

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How it is done?

• Requirements
• Align ADC (comparator) decisions
• Correct ADC output bit pattern
• Add digital data in a 1.5-bit fashion
• Output a 8-bit digital word
• Implementation
• Shift register using Delayed D flip flop
• Ripple carry adder

6
Main Block Diagram


A6
B6
A5
B7
A7
B5
A4
B4
A3
B3
A2
B2
A1
B1
CLK1
SHIFT REGISTER
CLK2
Ripple Carry Adder
CLK2
Output register
D2
D1
D0
D7
D6
D5
D4
D3
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Shift register to align ADC decisions
STG -1
STG -2
STG -3
STG -4
STG -5
STG -6
STG -7
DFF
CLK1
DFF
DFF
CLK2
Shift register using D flipflop
DFF
CLK1
DFF
DFF
DFF
DFF
CLK2
DFF
CLK1
DFF
DFF
DFF
DFF
DFF
DFF
CLK2
DFF
CLK1
DFF
DFF
DFF
DFF
DFF
DFF
DFF
CLK2
RIPPLE CARRY ADDER
8


SHIFT REGISTER TEST
BENCH
SHIFT REG
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ALIGNING OF 14 BITS WITHIN 31/2 CLK
11
Digital correction logic
STAGE - 1
A7
B7
STAGE - 2
A6
B6
STAGE - 3
B5
A5
B4
A4
STAGE -4
Concept of Digital Correction

B3
A3
STAGE - 5
STAGE -6
B2
A2
A1
B1
STAGE 7


D7 D6 D5 D4 D3
D2 D1 D0



Z D Y B XOR C X A BC (CARRY BIT)
A
B
C
D

X Y Z
Mathematical analysis Of Digital Correction
12
Logic Equations used for RCA

• Total gate delay for RCA
• D0
  B1
• C0 A2 A1B2 D1 A1 XOR B2
• C1 B3C0 A3 D2 C0 XOR B3
• C2 B4C1 A4 D3 C1 XOR B4
• C3 B5C2 A5 D4 C2 XOR B5
• C4 B6C3 A6 D5 C3 XOR B6
• D6
  C4 XOR B7
• D7
  B7C4 A7
  

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RIPPLE CARRY ADDER
CARRY BIT
A BC
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SS With worst case for 4.5v 85C
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The delay in SS with worst case is 6.34ns
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SIMS RESULTS FOR DIFFERENT CORNERS FOR RCA
5.5 v
0
TT
SS
FS
FF
SF
5.0v
4.5v
27
0
85
0
27
85
27
85
4.65n
3.97n
6.34n
5.38n
4.94n
5.44n
4.63n
4.26n
4.73n
3.70n
4.02n
3.36n
2.89n
2.69n
4.60n
3.92n
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ALIGNING OF 14 BITS WITHIN 31/2 CLK
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Error Correction Logic
A7B7 A6B6 A5B5 A6B6 A4B4 A3B3 A2B2 A1B1 D7 D6 D5 D4 D3 D2 D1 D0
01 01 01 01 01 01 01 01 1 1 1 1 1 1 1 1
01 01 01 01 01 01 01 10 0 0 0 0 0 0 0 0
11 11 11 11 11 11 11 11 0 0 0 0 0 0 0 1
10 10 10 10 10 10 10 10 0 1 1 1 1 1 1 0
10 10 10 10 10 10 10 01 0 1 1 1 1 1 0 1
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SHIFT REGISTER WITH RCA AND OUTPUT REGISTER
SHIFT REGISTER
RCA WITH OUTPUT REG
22
30n
35n
Pulse width linear input to shift reg
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Conclusion

• 14 bits coming from the comparator are aligning
  with the help of the shift register within 41/2
  clock cycle.
• Ripple carry adder takes 6.34ns for worst case
  condition which is fast enough to get desired
  output
• Error correction logic is working for different
  combination of input bits.