SST-1%20Data%20Acquisition%20

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SST-1 Data Acquisition Control

• H D Pujara
• Institute for Plasma Research
• pujara_at_ipr.res.in

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Institute for Plasma Research
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Plan of the Talk
Brief Introduction of SST-1
Objective of data acquisition and Control
Timing System PXI CAMAC based Data Acquisition
system Major Constituents of Control
systems Software aspects
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Indian Tokamaks
ADITYA SINP Tokamak Major Radius
R0 0.75 m 0.30 m Minor
Radius a 0.25 m 0.075 m Toroidal
Field BT 1.50 T 2.00 T
Plasma Current Ip 250 kA 75
kA Pulse Duration ? 250 ms
20-30 ms Plasma Cross-section Circular
Circular Configuration Poloidal Limiters
Poloidal Limiters Coils Type (TF
PF) Copper Water cooled Copper Current
Drive Heating Ohmic Transformer Ohmic
transformer (Air Core) (Iron Core)
Vacuum vessel Vessel with Electrical
break Conducting Shell Design
Fabrication Indigenous M/S Toshiba, Japan
Installation 1989 1987
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SST1 MACHINE PARAMETERS MAJOR RADIUS
1.1M MINOR RADIUS 0.2
M ELONGATION 1.7-2 TRIANGULARITY
0.4-0.7 TOROIDAL FIELD 3T PLASMA
CURRENT 220 kA. ASPECT RATIO
5.2 SAFETY FACTOR 3 AVERAGE DENSITY
1X 1013cm-3 AVERAGE TEMP. 1.5
keV PLASMA SPECIES HYDROGEN PULSE LENGTH
1000s CONFIGURATION DOUBLE NULL
POLOIDAL DIVERTER HEATING CURRENT DRIVE
LOWER HYBRID 1.0 MW NEUTRAL BEAM 0.8
MW ICRH 1.0 MW TOTAL INPUT POWER 1.0
MW FUELLING GAS PUFFING
ISOMETRIC CUT- VIEW OF SST-1
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SUBSYSTEMS OF SST-1
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MACHINE PARAMETERS
MAJOR RADIUS 1.1m
MINOR RADIUS 0.2 m
ASPECT RATIO 5.5
ELONGATION 1.7-2
TOROIDAL FIELD 3T
TRIANGULARITY 0.4-0.7
PLASMA CURRENT 220 kA
PULSE LENGTH 1000S
AVERAGE DENSITY 1X 1013cm-3
AVERAGE TEMP. 1.5 keV
PLASMA HYDROGEN
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Vacuum Subsystem

• Vacuum Vassal made up of
• 16 Wedge shape sections
• 16 Interconnection ring
• Cryostat
• Pumping system
• Gas Feed System

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TOP PORT
VACUUM VESSEL MODULE

• VESSEL SECTOR 1
• INTERCONNECTING RING 1
• TOP VERTICAL PORT 1
• BOTTOM VERTICAL PORT 1
• RADIAL PORT 1
• RADIAL PORT FLANGE 1
• RADIAL PORT BLANKING
• FLANGE 1

VESSEL RING
VESSEL SECTOR
RADIAL PORT
PORT FLANGE
BLANKING FLANGE
BOTTOM PORT
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• SST1 CRYOSTAT
• Cryostat Parameters
• Vertical Height 2.6 m
• Outer Diameter 4.4 m
• Inner Diameter 0.355 m
• Wall Thickness 10 mm
• Total Surface Area 59 m2
• Total Volume 39 m3
• Total Weight 4520 kg
• Material SS 304L

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SST-1 MAGNET SYSTEM

• Requirements
• Confinement, Shaping and Equilibrium Fields
• Ohmic Flux Storage
• Feed-Back Control

• Supercondcting Magnets
• Toroidal Field (TF) Coils 16 Nos.
• Poloidal Field (PF) Coils 9 Nos.

• Copper Magnets (Water Cooled)
• Ohmic Transformer (TR) Coils 7 Nos.
• Poloidal Field (PF ) Coils ( in-Vessel) 2 Nos.
• Position Control Coils ( in-Vessel) 2 Nos.

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SST-1 Poloidal Field Coils

• Design Drivers
• Support single double null equilibria with wide
  range of Triangularity ( 0.4-0.7), Elongations (
  1.7-1.9), li (0.75 -1.4), ?p ( 0.01-0.85)
  slot divertor configuration
• Limiter operation during Plasma current ramp up

Parameters of PF Coils
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Gas feed System

• Plasma of Hydrogen gas
• Gas fueling during normal operation of 1000 sec.
• Uniform gas distribution.
• 28 pizo electric gate valve around the machine.
• Plasma Density control for constant density
• Online feed control by adjusting gas flow.

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Auxiliary Heating system

• Lower hybrid current drive (LHCD) system.
• - Responsible for driving the plasma and
  maintain current for 1000 sec.
• -One Megawatts of CW power at 3.7Ghz
• -Two High Power Klystron, each delivering 500KW
• - Ohmically driven Ip (110KA to 220Kam) will be
  Taken over by LHCD
• Circular plasma will be shaped with PF coils
• Will be lunched through redial port to a grill of
  64 wave guides
• Pressured transmission line to avoid the Breakdown

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Ion Cyclotron Resonance Freq.

• Tetrode based 1.5 MW ICRF system.
• Frequency of operation 20 to 92 MHz
• Temp of 1.0KeV
• Lunched through radial port, four antennas 375Kw
  each
• Pressurized 90 meter long 9 inch dia 50 ohm
  transmission line
• Online stub and frequency matching for optimum
  power transfer.
• Reflected power will be compensated with hike in
  input RF power.

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Electron Cyclotron Resonance Freq. Heating.

• Gyrotron Based 200KW CW _at_ 84GHz
• Focused Microwave beam of 18 mm radius.

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SST1 ECRH SYSTEM

• Objectives
• Pre-Ionisation Plasma start up
• Electron Cyclotron Heating to assist Current
  drive during LHCD

• Main Parameters
• Gyratron Frequency 82.6 GHz
• Output Power 200 kW CW
• Output Mode HE-11
• Operating TF Field
• Fundamental 3 T
• 2nd Harmonic 1.5 T
• Exit dimensions of Waveguide 63.5 mm

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SST-1 LHCD SYSTEM

Frequency 3.7 GHz. Power ( 2 klystrons each
of 500 kW CW) 1 MW Antenna type Grill of
subwaveguides 32 x 2rows Periodicity (with
2mm thick septa) 9 mm Subwaveguide opening
76 x7 mm2 Design NII (at 90o phasing)
2.25 NII variation (from 40o to 60o phasing)
1.0 - 4.0 Klystron input power 10Watt
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Plasma Facing Components of SST-1

• Design Drivers
• Steady state heat and particle removal
• 1 MW power Input
• Surface temperature ? 1000 0C
• Baking up to 350 0C
• Electromagnetic forcesss during VDE, disruptions
  and halo currents
• Modularity

• Isostatically pressed, low ash content,Graphite
• Tiles mechanically attached to High strength
  copper alloy (CuZr Cu CrZr) backplate
• Cooling tubes (SS304) embedded in brazed to
  the back plates.

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PLASMA FACING COMPONENTS OF SST-1
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Objective and Requirements of DAS
SST-1 is a steady state device
The system must capable enough to acquire all
required physics information..
Due to continuous nature of operation no
physics information should be lost..
And no unnecessary data should be acquired.
Concept of event for data reduction, Scheduled
and un scheduled events.
If required must offer lossless acquisition..
Provide support for real time visualization of
data.
On line processing for Physics Information.
Remote operation, processing and viewing
GUI based local and synchronous operations.
Tagged with events for post processing and
viewing.
Distributed DAS for batter data managements
performance enhancement with growing tech
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How SST-1 DAS Differs
Most of the Tokamak operates in pulse mode
Discharge duration could be few seconds
Captures data during discharge. 
  Retrieves it later on for analysis
Display of data as a single trace.
Do not demand any need of viewing data during
discharge since discharge is limited for few
seconds
Generates manageable data during shot-10Mb or so
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However SST1 will be operated under steady State
for 1000 Seconds
Demands online viewing 1000 seconds 20 minutes,
cant wait till end of the pulse
Online processing to infer physics parameter like
Density, Plasma current
Demands large local buffers for storage
Generates large amount of data
Demands transfer to host-as fast as possible for
loss less acquisition
Tagging of events and time
Storage for post processing
These all puts significant effect on acquisition
instruments
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Above requirements poses many Technical problems
Large amount of data
Network load increases substantially
Storage requirements grows enormously
Processing needs also grows and demands faster
CPUs
Large buffers or Multi buffer schemes
Deterministic nature of network and minimum
latency
Here the root cause is LARGE AMOUNT OF DATA
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How one can reduce the data? EVENT DRIVEN
SAMPLING
  Acquire data at lower sampling rate during low
activity period
Change Sampling rate as and when important event
occurs
Revert-back to normal sampling rate after /\ t
If everything is sequential and pre determined
---window based acquisition
Event driven sampling
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How much reduction in data one can achieve in
Event base triggering?
          Depends on number of events, duration
of events.           Sampling rate during
event.           Base level Sampling
rate.           Depends on diagnostic and its
needs.  
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What are the problems caused by event driven
sampling Scheme?
  Each diagnostic has to identify the events, its
duration and required Sampling rate.         
Each sub-system like NBI, LHCD, ICRH etc. Has to
identify events.          Generation of events-
Electronics hardware.
Encoding of events- numbering of events.   
Distribution of events to various sub-systems and
digitizers, Its Time criticality .
                       Selection of digitizer
which can accepts such events triggering.        
   Time tagging of events while storing the
data.           Event recording- Sampling rate,
event etcs needs to be stored for post archival.  
This basically demands a very unique
timing/triggering system.
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Employ various diagnostics to study the various
parameters like
Electron Density
Bolo meters
Soft X-Ray radiation
Thomson scattering
Charge-exchange
Plasma Current
Langmiur Probes
Microwave Interferometer
Loop Voltage
Electron Temperature
Spectroscopy
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Diagnostics and Events
100ms Multiple window
Current Ramp up
LHCD / NBI ON
Gas puff
Current ramp down
Disruption
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Diagnostics and Data Volume
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Total of 250 Data channels demanding Continuous
Acquisition for all 1000 sec. _at_ 10Khz sampling
Generate 3.5 Gbytes of data.
Generate 3.5 Mbytes/sec
Total of 450 Channels at fast sampling rate
_at_1Mhz, event based
Number of schedule and unscheduled events about 5
Total Data 225 Mbyte on board
timing/triggering system
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Timing System
SST-1 is consists of various subsystems
Subsystems are Physically wide apart.
Time synchronization between the subsystem is
required for proper and reliable operation of
Experiment.
Exchange of events between sub systems is
essential for smooth operation. Deterministic
distribution within 5 micro sec
Common clock reference for tight simultaneity
between subsystem and central control.
Event based sampling to limit data volume and
not to lose the physics information.
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Constituents of Timing system
Master Control Unite (Event Sequencer
distributor) VME based CPU Fiber Optic
communication Link _at_100Mbits/sec Tree Structure
Event Encoder Module 8 Event Inputs 16 bit
code Fiber optic link with master unit
Timer Module Event Decoder Programmable Delay
Trigger generators. Reference Clock Fiber optic
link with master unit
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Available BUS Options
ISA 8bit, 16 bit, Max 8MB/s Limitation of slots
PCI 32Bit, 132Mbyte/sec
CPCI 32Bit 64Bit 132/256MB/s
PXI Extension of PCI, Sync. Clock, Trigger
lines, Local Bus EMI/EMC, Cooling, Pug Play,
VISA
VME 32/64Bit, 40/80MB
VXI 32Bit, 40MB/s 10MHz sync clock, Trigger
lines, Local Bus, Module ID, Resource manager,
EMI/EMC
IEEE1934 Serial Bus, 200/400Mbits
CAMAC
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Available BUS Options For Instrumentations
ISA 8bit, 16 bit, Max 8MB/s Limitation of slots
PCI 32Bit, 132Mbyte
CPCI 32Bit 64Bit 132/256MB/s
PXI Extension of PCI, sync. Clock, Trigger lines,
Local Bus EMI/EMC, cooling , P P VISA
VME 32/64Bit, 40/80MB
VXI 32Bit, 40MB/s 10MHz sync clock, Trigger
lines, Local Bus,Model ID, P P, Resource
manager EMI/EMC , VISA
IEEE1934 Serial Bus, 200M/400Mbits
CAMAC
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What is the solution Considering the data rate
generation as per the requirements
For Slow Diagnostics Demanding Continuous Loss
less acquisition. Volume of data generation is
less per sec FIFO/Dual Ported RAM buffer Fast
back plane Data streaming to disk
For Fast Diagnostics demanding higher sampling
rate Data must be stored on Onboard
Memory Multi Buffer or Segmented memory for
different events
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Opted for
Fast Diagnostics CAMAC based stand alone system
has been chosen. For this a ISA bus based 16 Bit
Crate Controller and a special digitizer
supporting multiple segments of memory for
Events has be developed in house.
PXI for Slow Diagnostics The PXI based system
has been chosen. The major reason of choosing
PXI is that it is based on the industry
standard PCI bus. For making it perfect for
instrumentations, the additional trigger lines,
local bus and a clock signal has been
incorporate. In addition the chassis
complies with EMC/EMI standard. All the PXI
module comes bundled with Plug and Play driver
for windows platform. The bus offers a transfer
rate of 132Mbytes _at_33MHz Fiber optic link to
host.
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Opted for
   CAMAC based- Computer Automated Measurement
And Control. Fast Diagnostics
PXI for Slow Diagnostics Data Streaming to the
disk
     VME For control applications
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PCI bus

• PCI bus developed by Intel.
• Introduced in 1993.
• 486 motherboards use PCI as well.
• Clearly is the Bus of the future

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PCI Highlights

• 32-bit bus that normally runs at a maximum of 33
  MHz
• Greater system performance ,with a maximum data
  transfer rate of 132MB/s
• Offers excellent expandability for
  high-performance peripheral devices
• investment spanning multiple CPU generations
• Processor independent

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Computer Bus Architecture
CPU
16-bit
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PCI bus

• 33 MHz, 32-bit, address
• lines and data lines are shared
• Memory (where cards live)
• IO (chip connection)
• Configuration
• Bios on bootup
• Each slot on the PCI bus
• has the configuration registers
• shown at the right.

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The PCI bus

• Wide Industry Support
• Plug and Play capability
• Thousands of software products
• 32-bit data transfers at 33 MHz (132 Mbytes/sec)
• PCI is a de facto standard
• Automatic Resource Allocation
• BIOS will normally "lock" the "PCI IRQ and DMA
  Settings"
• PCI IRQ and DMA Settings can also be set manually

But limited slots.
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Peripheral Sizes in PCI and CompactPCI
PXI/CompactPCI
PCI
Half Size
PCI boards can be redesigned to fit in
PXI/CompactPCI with littleor no electrical
changes.
3U

• Eurocard Packaging Proven over decades of use
  in industrial applications (VME, VXI,
  etc.) Defined by IEEE 1101 Standard

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PC Motherboard Controller Backplane
PC Motherboard with 4 PCI slots
CompactPCI 8-slotBackplane
CompactPCI EmbeddedController
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Electrical Extensions

System Controller
Star Trigger Controller
Peripheral
Peripheral
Peripheral
132 Mb/s, 33 MHz, 32-bit Computer Bus

• Integrated 8 Trigger Lines, 10 MHz reference
  clock, Star Trigger Bus
• Local Bus between adjacent slots 13 lines

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Mechanical Extensions

• Mandatory Active Cooling
• System-level environmental specificationsfor
  EMC, shock, vibration, and humidity
• Defined embedded controller location

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PXI/CompactPCI Form Factors
64-bit PCI and
J2
PXI Features
3U
PXI/CPCI
J1
32-bit PCI
6U Adapter Panel
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Software Extensions

• PXI speeds application development because
• PXI Controllers MUST support a standard software
  framework by including a pre-loaded OS
• Windows NT
• Windows 9x
• Peripherals modules MUST be supplied with a WIN32
  Device Driver

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PXI and PC Software is Identical

• Operating systems and application software run
  unchanged on PXI systems
• Configuration tools recognize PXI modules as PCI
  devices

We ported from a desktop PC to PXI without
changing any code" - Len Burczyk, Los Alamos
National Laboratories
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PXI Also Works with Other Standards
PXI Chassis
GPIB
MXI
CompactPCI
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Controller Option

• Embedded controllers
• Most compact solution
• Modular
• Pentium and Pentium III Class

• Remote MXI-3 controllers
• Short or long 200 meter distance
• cupper or fiber connectivity 1.2Gbits/s
• can sustain data transfers at over 80 Mbytes/s
• Fully transparent
• Low cost

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MXI-3 Benefits

• More slots for PCs and PXI/CompactPCI
• Very high performance serial fiber link 1.2GB/s
• Easy to integrate software transparent
• 200 meter L O N G distances
• Low cost

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Front_end Electronics with built in Intelligence
for Plasma Diagnostics.
During operation no entry to hall
Remote setting of front end electronics is
required
Signal Originating from diagnostics has large
dynamic ranges
Dynamic control of various settings of Front_end
Electronics Gain, BW
Shielded twisted pair Cables
Opto Isolations
CANBuse base system, multi drop, serial bus
_at_1MBits/s, msg exchange with priority, priority
and address is part of msg,received by all, act
if req.
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PXI Based Lossless Continuous Data Acquit ion
Platform Windows2000
Development Tool LabWindows/CVI
Data Socket based Client/Server Architecture
Direct Data Streaming to Hard Disk
1.2GB/s Fiber Optic Link
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Server Architecture
dSampRate 1200000 iHalfBufsToRead iteration
GetCtrlVal (panelHandle, PANEL_LST1, SampRate1)
ulCount1 SampRate1Num_of_Channel2 piBuffer1
(short )malloc(ulCount12) piHalfBuffer1
(short )malloc(ulCount1)
DS_ControlLocalServer (DSConst_ServerLaunch)
Init_DA_Brds (1, brd1) Init board
AI_Configure (1, -1, 2, 10, 0, 1)
DS_Open ("dstp//202.41.112.140/dataport1",
DSConst_Write, DSCallback, NULL, dsHandle)
DAQ_DB_Config(iDevice1, iDBmodeON)
SCAN_Start(iDevice1, piBuffer1, ulCount1,
iSampTB1, uSampInt1, iScanTB1, uScanInt1)
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Wihle (loops lt100)
STOP
DS_SetAttrValue (dsHandle, "Samp_Rate1",
CAVT_FLOAT, SampRate1, 0, 0)
DAQ_DB_HalfReady(iDevice1, iHalfReady1,iDAQstop
ped)
if ((iHalfReady1 1)
DAQ_DB_Transfer(iDevice1, piHalfBuffer1 fwrite
(piHalfBuffer1, 2,ulPtsTfr, ffp1) PlotY
(panelHandle, PANEL_GRAPH DS_SetDataValue
(dsHandle, CAVT_SHORTCAVT_ARRAY DS_Update(dsHandl
e)
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Client
DS_Open (URL, DSConst_ReadAutoUpdate,
DSCallback, NULL, dsHandle)
DS_EVENT_STATUSUPDATED DS_EVENT_DATAUPDATED
hr DS_GetAttrType (dsHandle, "Samp_Rate1",
type))
If (data type matches)
DS_GetAttrValue (dsHandle, "Samp_Rate1", type,
SampRate1)
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DS_GetDataType
If (data type matches
DS_GetDataValue (dsHandle, type, dataArray
Integrate(input_integrater
PlotY (mainPanel, MAINPNL_GRAPH)
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Observed Performance of PXI onWindows2000
Data Acquisition Module with 16 Channels, 12 Bit
ADC, supporting aximum1.2Msamaples/sec. 2 channel
DAC, 2 Channel of counter/timers and 8 Lines of
gital I/O. Such three modules. ( 48 Ch of Analog
In, 6 ch of Analog out, 24 I/O nd 6 counter
timers)
Continuous Data Acquisition.... Acquisition
Server (48 channel _at_ 10 kHz, writing to file for
1000 sec. and pushing the all 48 channel on
network using Data Sockets )
Synchronized Continuous Acq. with start trigger
(One common start trigger  to    one module and
the same is applied to  rest by the back plain) 
Single Shot application..
On fly sampling rate changing in case of
Scheduled Event triggering.
MultiTrigger In case of event based sampling 100
events with time gap of 70msec can be acquired
with ploting of the data and with out plot the
subsequent time gap can be 15msec. (This was
tried with pre/post trigger facility
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Following performance was very recently
HP Vectra P-III _at_1.2 GHz supports 96 channels
acquisition _at_10KHz with pushing all data no
network and storing it on hard disk with few
channels plotting on local machine.
Embedded PC of NI P-II _at_1.2GHz working supports
up 96 channel _at_20KHz.
This is double the channel handling capacity
compare with PCL machine working at P-III _at_500MHz
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CAMAC based Data Acquisition for fast diagmnostics
Platform Windows2000
Development ToolLabWindows/CVI
Data Socket based Client/Server Architecture
On board memory, Multiple segments
Standalone CAMAC system
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Crate Controller
16 bit parallel crate controller
Data transfers under PIO and DMA mode
Device Driver with DAM for Windows2000 platform
Differential line drivers to support the longer
distance
ISA bus
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CAMAC Digitizer for Fast Diagnostics
Design our own CAMAC Module
Independent 8 bit ADC per channel, /- 5 V Four
channel per module 512KB memory per
channel Single width CAMAC module Digitizing rate
up to 1MHz Selectable pre/post trigger samples
Selectable segment size
Facility for Onfly Reading
Supports Continuous, Transient and Monitoring Mode
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ON FLYREAD BUFFER
CAMAC READ LINES
INPUT SIGNAL
HF
FIFO
CLOCKGENERATOR
FF
EF
A D C
LATCH
R
CONTINUOUSREAD BUFFER
INSTRUMENTATION AMPLIFIER
CLOCKDIVISION
CLK
TRANSIENTREAD BUFFER
EN
Function Decoder
W
CLOCK
CLOCKSELECTION
BUF1
HF
FF
R
CLOCK
RAM
OR
START TRIGGER
ENB1
OR
SAMPLINGCLOCK
BUF2
COMPARATOR
NOT
INPUT SIGNAL
A0-A14
R/W
ENB2
CLOCKDIVISION
ADDRESSCOUNTER
LATCH
DAC
CONTROL LOGIC
CAMACWRITELINES
CAMAC DIGITIZER
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START
RESET
SELECT SAMPLING RATE
MODE
CONTINUOUS MODE
TRANSIENT MODE
START DIGITIZING
START DIGITIZING
MONITORING MODE
START TRIGGER
START DIGITIZING
START TRIGGER
STORE DATA IN FIFO RAM
READ DATA FROM ADC ON-FLY
READ DATA FROM FIFO ON LAM
IS STOP TRIGGER
NO
STOP
IS STOP TRIGGER
YES
NO
ON FULL FLAG (FIFO) READ DATA FROM FIFO
FUNCTIONAL SEQUENCE OF CAMAC BASED DUAL RATE
DIGITIZER
YES
READ DATA FROM RAM
STOP
STOP
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FOUR IDENTICAL CHANNELS
HF
R
ANALOG INPUT
RAM
FIFO
CAMAC READ LINES
READ BUFFER
ADC
INSTRUMENTATION AMPLIFIER
CLK
WR
R/W
CLOCK
ADDRESS COUNTER
HF
CLOCK GENERATOR
CLOCK
R
OR
CLOCK DIVISION
OR
TRIGGER
OR
START
CLOCK SELECTION
OR
SAMPLING
CLOCK
OR
ACQUISITION
SAMPLING CLOCK
WINDOW
CONTROL LOGIC
HIGH SPEED CAMAC DIGITIZER
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Objective and Requirements of Control
Since SST-1 is consist of many subsystem the
major objective is to ensure reliable and smooth
operation.
Provide Integrated interactive Remote control
environment
Proper sequencing of subsystem for synchronized
operation
Safety interlocks and fail safe measure under
normal and abnormal conditions
Fast real time control of Plasma shape and
position.
Interactive strategic control during the pulse.
Configuring and downloading operation parameters
to various subsystem
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Implementation approach
Hierarchical distributed control system.
Supervisory central control at the top
Supervising subsystems and exchanging status ,
parameters and commands
Individual subsystems are directly controlled and
monitored by its own dedicated intelligent
control system
For quicker and faster actions Interlocks and
safety measures will be exercised by individual
subsystem
For batter and Efficient managements of the
system entire control activity has been divided
in following groups
Machine Control system
Diagnostic Control System
Discharge Control System
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Machine Control
All the subsystem doing routine tasks like
monitoring temp, water flow, vac pressure etc.
are covered under machine control.
Status and heath of all the subsystem will be
monitored under the Machine control
Down load of limit values and summary of status
from subsystem
Power Supply System Status of switch Yard TF
currents on/off, limit values, TF current
profiles
Vacuum System Control of vacuum pumping
system, sequencing gate valves, Partial
pressure measurements Status of various
components
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Water Cooling System Number of cooling system
for passive plate divertor Copper coils OT
cooling system temp alarm and limit
sets water flow water pressure etc
Discharge cleaning system On/off, Discharge
currents
Cryogenics status
Coil Protection and Monitoring system Status Lim
it values
Auxiliary Heating system Status of LHCD, ICRH, NBI
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Dynamic Discharge control System
Due to long discharge time.. One has a option of
changing the strategy online depending upon
the situations
Scheduled discharge phases can be dynamically
changed
Includes Plasma Current, Shape, Position and
Density Control
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Position and Shape Control
Target system PowerPC Real Time OS.
VxWorks Reflective Memory for real time data
sharing
Position Control will be fast Time scale of the
order of 100 micro sec. Changing current in
copper conductor active feed back coil
Plasma Position and Shape Control Common
algorithm to estimate the Plasma Position and
Shape Based on Function Parameterization code
Relatively on slow time scale Constraint due to
Super conductor PF Coils Rapid change of I is not
permitted through PF due Quench And L/R ratio
Signal from 48 Mag probes, Plasma Currents ,
Flux loops and coil currents to determine the
shape Position. Error in shape will be
translated into correction PF current
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Density and Plasma Current Control
Electron density 10ms time scale
Ref. Density
Gas Feed Controller
Piezo gate Valve
Microwave Interferometer
Plasma
Fringe Counter
Plasma Current will be controlled By controlling
the LHCD power Rogowski coils / Hall sensors 1 ms
correction time scale
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Control Overview
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Software H/W
Software Development Tools Lab
Windows/CVI LabView TCL/TK MSSQL ORACLE
EPICS
Platforms. Windows Linux Real-time
Linux VxWorks
Hardware CAMAC PXI VME Reflective Memory
Processor Pentium PowerPC
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Thanks.