CMOS Circuit Design, Layout and Simulation

1
CMOS Circuit Design, Layout and Simulation
Sam Burke UCSB HEP Group
2
References

• Text
• CMOS Circuit Design, Layout, and Simulation by
  R. J. Baker, Li and Boyce IEEE Press Oct 2002
• ISBN-81-203-1682-7
• URL
• http//cmosedu.com/cmos1/book.htm

3
The Well

• P Type Wafer
• boron acceptor atoms (25 ohmcm)
• Transistors
• Nmos Transistors on p-substrate
• Pmos Transistors on n-well
• Diode
• formed between the n-well and p-substrate

4
Historical Methods

• Point Contacts
• 1948
• Grown Junctions
• 1950
• Alloy Junctions
• 1952
• Planar Technology or Junction Technology
• 1953

5
A Little History
6
Patterning

• Start with clean bare wafer
• Grow Oxide
• wet oxide
• dry oxide
• Apply Resist
• Photo-resist pattern
• Expose
• Develope
• Etch to remove oxide
• Ready for Diffusion

7
Growing an N-Well

• Donor Atom Diffusion
• Donor valance5
• Phosphorus
• Si valance4
• N Well Resistivity
• 0.75 ohmcm

8
The N-Well
9
The Well Resistor

• Rp/tL/W
• RResistance
• presistivity
• RRsqL/W
• Rsqsheet resistance (ohm/square)
• For N-Well
• p0.75ohmcm
• t3um L100um
• W10um
• R2500100/1025kohms

10
Si Resistivity

• Experimental Data
• N-Type donor concentration shown for resistor
  example
• Ref Grove, A.S Physics and Tech - -

11
N-Well Cross Section
12
L-Edit

• Demo the creation of an N-Well using L-Edit
• Error checking

13
Design Process
14
Well and Contacts

• N-Well contact on left
• metal1
• active
• Bulk contact on right
• metal1
• active
• P Implant

15
PN Junction Depletion

• Carrier drift

16
PN Junction Voltage
17
Diode Junction Capacitance
18
Diode V/I Equation
19
Forward Biased Diode
20
S-Edit
21
T-Spice
22
Net List of Diode Circuit
23
Diode Storage Time