Computer Architecture Project

1
Computer Architecture Project

• 55035 Computer Architecture
• Spring 2011

2
Minimum CPU Requirements

• Initial Requirements
• Minimum operand size is 8 bits (1 byte)
• memory locations is gt65536 (16 bits needed for
  address)
• Data instructions ADD, SUB, LOAD, STORE, TEST,
  (PUSH, POP)
• Prog. cont. inst. JUMP BR relative
  uncond./conditional, CALL, RET

3
Large System Block Diagram
Control Unit
Datapath
Control Inputs
Data Outputs
Control
Status
Control Outputs
Data Inputs
4
System Parameters

• What is the primary memory / operand size?
• If gt 8 bit operands, is data addressing to word
  or byte?
• Does the data bus have a shared or separate
  address/data bus?
• Is the data bus protocol synchronous or
  handshake?
• Is instruction/data memory shared or separate?
• Is I/O separate or memory mapped?

5
CPU Architecture

• Is the CPU CISC or RISC?
• If CISC, is it single ACC, multiple reg. ______,
  stack or ______________?
• If RISC, how many registers?
• Is data organization big-endian or little-endian?
• For interrupts, are the ISR addresses fixed or
  vectored?

6
Instruction Set Architecure

• Is the most complex instruction to be 1, 2, or 3
  operand?
• What addressing modes are to be used?
• 0 - Implied 4 - Memory direct
• 1 - Immediate 5 - Memory indrect
• 2 - Register direct 6 - Relative
• 3 - Register ind. 7 - Indexed
• 8 - _____________ 9 - _____________
• A - _____________ B - _____________

7
ISA (cont.)

• Do we implement a LIFO stack? Yes / No
• If so, does the stack grow up or down?
• If not, how do we save the return address for
  CALL and Interrupt?

8
Additional Features