Independence Fault Collapsing

1

• Independence Fault Collapsing
• and Concurrent Test Generation

Masters Defense Alok S. Doshi Dept. of ECE,
Auburn University
Thesis Advisor Vishwani D. Agrawal Committee
Members Victor P. Nelson, Charles E.
Stroud Dept. of ECE, Auburn University January
25, 2006
2
Outline

• Introduction
• Problem Statement
• Motivation
• Background
• Contributions of this Research
• Fault Classification and Independent Faults
• Independence Fault Collapsing
• Concurrent Test Generation
• Simulation Based Techniques
• Results
• Conclusions and Future Work

3
Problem Statement

• To find a minimal test vector set to detect all
  single stuck-at faults in a combinational circuit.

4
Motivation
ATPG Tests
Hitec1 10
Fastest2 7
Gentest3 7
Atalanta4 6-9
a
x
b
c
y
d
e
C17 - ISCAS85 Benchmark Circuit
Minimum 4
1 T. M. Niermann and J. H. Patel, HITEC A Test
Generation Package for Sequential Circuits,
Proc. European Design Automation Conference, Feb.
1991, pp. 214-218. 2 T. P. Kelsey, K. K. Saluja,
and S. Y. Lee, An Efficient Algorithm for
Sequential Circuit Test Generation, IEEE Trans.
Computers, vol. 42, no. 11, pp. 1361-1371, Nov.
1993. 3 W. T. Cheng and T. J. Chakraborty,
Gentest An Automatic Test Generation System for
Sequential Circuits, Computer, vol. 22, no. 4,
pp. 4349, April 1989. 4H. K. Lee and D. S. Ha,
Atalanta An Efficient ATPG for Combinational
Circuits, Tech. Report 93-12, Dept. of
Electrical Eng., Virginia Poly. Inst. and State
Univ., Blacksburg, Virginia, 1993.
5
Motivation

• 4-bit ALU (74181)

ATPG Tests
Gentest 42
Fastest 37
Hitec 36
Atalanta 23-39
Minimum 12
6
Background

• Problem of finding a minimal test
• Static compaction cannot guarantee optimality.
• Dynamic compaction is complex.
• Solution Target both faults F1 and F2 at the
  same time to find a single test.

.
.
.
T(F2)
T(F1)
Test set for fault F2
Test set for fault F1
v2
v1
v3
7
Outline

• Introduction
• Problem Statement
• Motivation
• Background
• Contributions of this Research
• Fault Classification and Independent Faults
• Independence Fault Collapsing
• Concurrent Test Generation
• Simulation Based Techniques
• Results
• Conclusions and Future Work

8
Fault Classification
T(F1)
T(F1) T(F2)
T(F2)
F1 and F2 are equivalent.
F1 dominates F2.
T(F1)
T(F2)
T(F1)
T(F2)
F1 and F2 are independent.
F1 and F2 are concurrently testable.
9
Definitions

• Independent Faults5
• Two faults are independent if and only if they
  cannot be detected by the same test vector.
• Concurrently-Testable Faults
• Two faults that neither have a dominance
  relationship nor are independent, are defined as
  concurrently-testable faults.

5 S. B. Akers, C. Joseph, and B. Krishnamurthy,
On the role of Independent Fault Sets in the
Generation of Minimal Test Sets, in Proc.
International Test Conf., 1987, pp. 1100-1107.
10
Structural Independences
sa1
sa1
sa1
sa0
sa1
sa0
sa1
sa1
sa1
sa0
sa0
sa0
sa1
sa1
sa0
sa0
sa0
sa0
sa0
sa1
11
Implied Independences

• Equivalence implied independence
• If two faults are equivalent then all faults
  that are independent of one fault are also
  independent of the other fault.
• Dominance implied independence
• If one fault dominates a second fault then all
  faults that are independent of the first fault
  are also independent of the second fault.

12
Functional Independences
13
Example Circuit
2-1
4-1
a
x
5-1
1-1
b
3-1
7-1
11-1
c
y
d
6-1
10-1
9-1
e
8-1
C17 - ISCAS85 Benchmark Circuit
6 R. K. K. R. Sandireddy and V. D. Agrawal,
Diagnostic and Detection Fault Collapsing for
Multiple Output Circuits," in Proc. Design,
Automation and Test in Europe (DATE) Conf., Mar.
2005, pp. 1014 - 1019.
14
Independence Matrix and Graph
F 1 2 3 4 5 6 7 8 9 10 11
1 0 1 1 1 1 1 0 0 1 0 1
2 1 0 0 1 1 0 1 0 0 0 1
3 1 0 0 0 1 1 1 1 0 1 1
4 1 1 0 0 1 0 1 0 0 0 1
5 1 1 1 1 0 0 0 1 1 1 0
6 1 0 1 0 0 0 1 1 1 0 0
7 0 1 1 1 0 1 0 1 1 0 0
8 0 0 1 0 1 1 1 0 1 1 1
9 1 0 0 0 1 1 1 1 0 1 1
10 0 0 1 0 1 0 0 1 1 0 1
11 1 1 1 1 0 0 0 1 1 1 0
C17 - ISCAS85 Benchmark Circuit
15
Outline

• Introduction
• Problem Statement
• Motivation
• Background
• Contributions of this Research
• Fault Classification and Independent Faults
• Independence Fault Collapsing
• Concurrent Test Generation
• Simulation Based Techniques
• Results
• Conclusions and Future Work

16
Independence Fault Collapsing

• The aim of independence fault collapsing is to
  collapse the independence graph into a
  fully-connected graph such that all or most
  faults in a given node will have a single test.
• These nodes will then serve as fault targets for
  Automatic Test Pattern Generation (ATPG).

17
Cliques
18
Clique

• A clique is defined as a fully-connected
  subgraph, i.e., a subgraph in which every node is
  connected to every other node.
• A lower bound on the number of tests required to
  cover all faults of an irredundant combinational
  circuit is given by the size of the largest
  clique of the independence graph.

19
Degree of Independence

• Degree of Independence
• This is the number of edges attached to the
  fault node and is computed for the ith fault by
  adding all the elements of either the ith row or
  the ith column of the independence matrix.
• DI (ith fault) S xij S xji

N
N
j1
i1
20
Degree of Independence
Fault 1 2 3 4 5 6 7 8 9 10 11 DI
1 0 1 1 1 1 1 0 0 1 0 1 7
2 1 0 0 1 1 0 1 0 0 0 1 5
3 1 0 0 0 1 1 1 1 0 1 1 7
4 1 1 0 0 1 0 1 0 0 0 1 5
5 1 1 1 1 0 0 0 1 1 1 0 7
6 1 0 1 0 0 0 1 1 1 0 0 5
7 0 1 1 1 0 1 0 1 1 0 0 6
8 0 0 1 0 1 1 1 0 1 1 1 7
9 1 0 0 0 1 1 1 1 0 1 1 7
10 0 0 1 0 1 0 0 1 1 0 1 5
11 1 1 1 1 0 0 0 1 1 1 0 7
DI 7 5 7 5 7 5 6 7 7 5 7  
21
Similarity Metric

• Similarity Metric
• This is a measure defined for a pair of faults
  that determines how similar they are in their
  independence and concurrent-testability with
  respect to the entire fault set of the circuit.
• SIM (fault-i, fault-j) Nxij (1-xij) S
  xik-xjk

N
k1
22
Similarity Metrics
Fault 1 2 3 4 5 6 7 8 9 10 11
1 0 11 11 11 11 11 3 4 11 4 11
2 11 0 4 11 11 6 11 6 4 6 11
3 11 4 0 4 11 11 11 11 0 11 11
4 11 11 4 0 11 6 11 6 4 6 11
5 11 11 11 11 0 4 3 11 11 11 0
6 11 6 11 6 4 0 11 11 11 4 4
7 3 11 11 11 3 11 0 11 11 5 3
8 4 6 11 6 11 11 11 0 11 11 11
9 11 4 0 4 11 11 11 11 0 11 11
10 4 6 11 6 11 4 5 11 11 0 11
11 11 11 11 11 0 4 3 11 11 11 0
23
Similarity Metric of a Fault-Pair
Max. 0
Highly Dissimilar Highly Similar
Similarity metric of a fault-pair
Equivalent Independent (Group
together) (Group separately)
24
Step 1 Compute Degree of Independence (DI) for
All Faults
Fault 1 2 3 4 5 6 7 8 9 10 11 DI
1 0 1 1 1 1 1 0 0 1 0 1 7
2 1 0 0 1 1 0 1 0 0 0 1 5
3 1 0 0 0 1 1 1 1 0 1 1 7
4 1 1 0 0 1 0 1 0 0 0 1 5
5 1 1 1 1 0 0 0 1 1 1 0 7
6 1 0 1 0 0 0 1 1 1 0 0 5
7 0 1 1 1 0 1 0 1 1 0 0 6
8 0 0 1 0 1 1 1 0 1 1 1 7
9 1 0 0 0 1 1 1 1 0 1 1 7
10 0 0 1 0 1 0 0 1 1 0 1 5
11 1 1 1 1 0 0 0 1 1 1 0 7
DI 7 5 7 5 7 5 6 7 7 5 7  
25
Step 2 Order Faults by DI
Fault 1 3 5 8 9 11 7 2 4 6 10 DI
1 0 1 1 0 1 1 0 1 1 1 0 7
3 1 0 1 1 0 1 1 0 0 1 1 7
5 1 1 0 1 1 0 0 1 1 0 1 7
8 0 1 1 0 1 1 1 0 0 1 1 7
9 1 0 1 1 0 1 1 0 0 1 1 7
11 1 1 0 1 1 0 0 1 1 0 1 7
7 0 1 0 1 1 0 0 1 1 1 0 6
2 1 0 1 0 0 1 1 0 1 0 0 5
4 1 0 1 0 0 1 1 1 0 0 0 5
6 1 1 0 1 1 0 1 0 0 0 0 5
10 0 1 1 1 1 1 0 0 0 0 0 5
DI 7 7 7 7 7 7 6 5 5 5 5  
26
Step 3 Compute Similarity Metrics for All
Fault-Pairs
Step 4 Collapse the Graph
F 1 3 5 8 9 11 7 2 4 6 10
1 0 11 11 4 11 11 3 11 11 11 4
3 11 0 11 11 0 11 11 4 4 11 11
5 11 11 0 11 11 0 3 11 11 4 11
8 4 11 11 0 11 11 11 6 6 11 11
9 11 0 11 11 0 11 11 4 4 11 11
11 11 11 0 11 11 0 3 11 11 4 11
7 3 11 3 11 11 3 0 11 11 11 5
2 11 4 11 6 4 11 11 0 11 6 6
4 11 4 11 6 4 11 11 11 0 6 6
6 11 11 4 11 11 4 11 6 6 0 4
10 4 11 11 11 11 11 5 6 6 4 0
11
4
11
0
3
1
5
1,8
5,11
5,11,7
3
3,9
3,9,2
4
4,6
4,6,10
11
0
4
6
Similarity index for fault F for each existing
node i Max. SIM (F, kth fault of node i) where
k 1..K, and K is number of faults in node i.
27
Bounds on Number of Tests

• Nc lt Number of tests lt S
• where, Nc is the number of nodes in the
  collapsed graph (Nc Nc).
• and, ki is the number of faults in the ith node.
• For C17, 4 lt Number of tests lt 7.

Nc
ki
_
i1
2
28
Outline

• Introduction
• Problem Statement
• Motivation
• Background
• Contributions of this Research
• Fault Classification and Independent Faults
• Independence Fault Collapsing
• Concurrent Test Generation
• Simulation Based Techniques
• Results
• Conclusions and Future Work

29
Concurrent Test Generation

• Concurrent Test
• Given a set of target faults, a
  concurrent-test is an input vector that detects
  all (or most) faults in the set.

30
Concurrent D Algebra for 2-Input AND Gate
31
Concurrent Test Generation for C17
D2
D2
0
D23
2-1
D3
1
D3
3-1
D39
1
0
1
9-1
D9
1
D9
32
Concurrent Test Generation for C17
2-1
4-1
a
x
5-1
1-1
b
3-1
7-1
11-1
c
y
d
6-1
10-1
9-1
Fault Targets Test
  (a b c d e)
1,8 10010
3,9,2 01111
5,11,7 X1010
4,6,10 10101
e
8-1
33
Results (ALU 74181)
Node Number of faults Number of faults Number of faults Number of faults Number of faults Test vectors
no. Total Targeted Detected from Detected from Cumulative  
      this node other nodes coverage  
1 5 5 5 6 11 01001111010001
2 3 3 3 2 16 01001111110101
3 8 7 7 3 26 01011101000001
4 3 3 3 3 32 101x0101010000
5 5 3 3 4 39 10100101011000
6 6 6 6 2 47 11111000001001
7 7 4 4 3 54 11100000100000
8 14 11 11 1 66 11100110101011
9 8 6 5 1 72 10010100110101
10 8 4 3 2 77 1x101011101100
11 8 3 3 1 81 01010000101100
12 9 2 2 1 84 1x011110001100
34
Outline

• Introduction
• Problem Statement
• Motivation
• Background
• Contributions of this Research
• Fault Classification and Independent Faults
• Independence Fault Collapsing
• Concurrent Test Generation
• Simulation Based Techniques
• Results
• Conclusions and Future Work

35
Simulation-Based Techniques

• The functional dominance fault collapsing6, used
  prior to independence fault collapsing, is based
  on ATPG and is complex.
• The independence graph generation procedure is
  also based on ATPG.
• The use of concurrent D-algebra requires a new
  ATPG program that may not be readily available to
  a user.

6 R. K. K. R. Sandireddy and V. D. Agrawal,
Diagnostic and Detection Fault Collapsing for
Multiple Output Circuits," in Proc. Design,
Automation and Test in Europe (DATE) Conf., Mar.
2005, pp. 1014 - 1019.
36
Simulation-Based Independence Fault Collapsing

• Start with a fully-connected independence graph
  for an equivalence collapsed fault set
  (structural collapsing only), i.e., assume
  initially all faults are independent of each
  other.
• Simulate random vectors without fault dropping to
  remove edges between faults detected by the same
  vector. Stop the random vector simulation when a
  large number of vectors do not remove any new
  edges.
• Apply the original independence fault collapsing
  algorithm on the generated independence matrix.

37
Simulation-Based Independence Fault Collapsing
301
74181 4-bit ALU
38
Simulation-Based Concurrent Test Generation

• For each group, generate all test vectors for the
  first fault in the group.
• If the number of test vectors for a fault is
  large, use a subset (e.g., 250 maximum) of
  vectors.
• Simulate all faults in the group to select one
  vector that detects most faults in that group.
• If more vectors than one detect the same number
  of faults within the group, then select the
  vector that detects most faults outside the group
  as well.

39
74181 4-Bit ALU Result
Group number Number of faults in group Concurrent test vector
1 2 3 4 5 6 7 8 9 10 11 12 13 9 15 11 6 11 17 11 16 16 22 22 56 81 01100011111100 01101100000110 10100101111010 11011010100000 10110101011010 10100111101010 10010101001110 01000111101011 11100010010011 11011100110100 01010001100001 All 56 faults detected by eleven previously generated vectors 10101001110110
40
Outline

• Introduction
• Problem Statement
• Motivation
• Background
• Contributions of this Research
• Fault Classification and Independent Faults
• Independence Fault Collapsing
• Concurrent Test Generation
• Simulation Based Techniques
• Results
• Conclusions and Future Work

41
Concurrent ATPG Results
Circuit No. of concurrent groups Concurrent ATPG Concurrent ATPG Single-fault ATPG Single-fault ATPG Single-fault ATPG Single-fault ATPG
Circuit No. of concurrent groups Vectors CPU s Atalanta Atalanta Best known Best known
Circuit No. of concurrent groups Vectors CPU s Vectors CPU s Vectors CPU s
1-b adder 2-b adder 4-b adder 8-b adder 16-b adder 32-b adder 4-b ALU c17 c432 c499 c880 c1355 c1908 c2670 c3540 c5315 c6288 c7552 5 5 5 7 7 7 13 4 30 52 24 84 106 81 107 92 23 190 5 5 5 7 9 11 12 4 34 52 29 84 111 92 130 104 25 198 0.085 0.092 0.103 0.182 3.3 9.7 11.4 0.082 10.4 14.6 23.3 34 49.6 57.6 119.6 216.3 158.1 360.7 5-7 7-9 8-11 10-15 13-22 17-25 22-40 6-9 49-77 54-68 52-106 85-109 118-173 106-192 147-263 114-224 32-48 209-358 0 0 0 0 0.017 0.050 0.033 0 0.083 0.033 0.133 0.1 0.5 1.2 1.9 0.733 4.7 5.283 5 5 5 5 5 5 12 4 27 52 16 84 106 44 84 37 12 73 - - - - - - - - 15 0.1 21.9 0.9 88.1 47.1 174.5 748.6 347.7 663.8
Sun Ultra 5 Pentium Pro PC
Hamzaoglu and Patel, IEEE-TCAD, 2000
42
Number of Vectors for Increasing Circuit Sizes
(100 Stuck-at Coverage)
Single-fault ATPG (no compaction)
Concurrent ATPG
Minimum achieved! (dynamic compaction)
1-bit c7552 adder
43
CPU Seconds for Increasing Circuit Sizes (100
Stuck-at Fault Coverage)
Concurrent ATPG
Minimum achieved! (dynamic compaction)
1-bit c7552 adder
44
Outline

• Introduction
• Problem Statement
• Motivation
• Background
• Contributions of this Research
• Fault Classification and Independent Faults
• Independence Fault Collapsing
• Concurrent Test Generation
• Simulation Based Techniques
• Results
• Conclusions and Future Work

45
Conclusions

• Concurrent test generation produces compact tests
  when combined with independence fault collapsing.
• ATPG and set covering problems have exponential
  time complexities. Hence, we cannot expect
  absolute optimality for large circuits.
• The concurrent ATPG procedure gives significantly
  smaller, and sometimes the optimum, test sets.

46
Future Work

• There is scope for improving the simulation-based
  algorithms for independence fault collapsing and
  concurrent test generation.
• Can be made more dynamic.
• Concern about memory requirement.
• Implement an ATPG program using the concurrent D
  algebra.

47
Future Work Another Collapsing Technique
11
4
11
3
5
F 1 3 5 8 9 11 7 2 4 6 10
1 0 11 11 4 11 11 3 11 11 11 4
3 11 0 11 11 0 11 11 4 4 11 11
5 11 11 0 11 11 0 3 11 11 4 11
8 4 11 11 0 11 11 11 6 6 11 11
9 11 0 11 11 0 11 11 4 4 11 11
11 11 11 0 11 11 0 3 11 11 4 11
7 3 11 3 11 11 3 0 11 11 11 5
2 11 4 11 6 4 11 11 0 11 6 6
4 11 4 11 6 4 11 11 11 0 6 6
6 11 11 4 11 11 4 11 6 6 0 4
10 4 11 11 11 11 11 5 6 6 4 0
6
7
7, 1
6, 5, 11
6, 5
7, 1, 10
8
9
9, 3, 2
8, 4
9, 3
11
4
4
0
11
6
Fault Targets Test (a b c d e)
6, 5, 11 01100
7, 1, 10 10011
8, 4 10100
9, 3, 2 01111
48

• Thank You!