CSE 140 Lecture 16 System Designs II

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CSE 140 Lecture 16System Designs II

• Professor CK Cheng
• CSE Dept.
• UC San Diego

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System Designs

1. Methodology
2. Hierarchy
3. Flow and Process
4. Technology-Oriented Construction

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Design Process

• Describe system in programs
• Data subsystem
• List data operations
• Map operations to functional blocks
• Add interconnect for data transport
• Input control signals and output conditions
• Control Subsystem
• Derive the sequence according to the hardware
  program
• Create the sequential machine
• Input conditions and output control signals

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Example Multiplication

• Input X, Y
• Output Z
• Variable M, i
• Mlt0
• For in-1 to 0
• If Yn-11, MltMX
• Shift Y left by one bit
• If i ! 0, shift M left by one bit
• ZltM

• Arithmetic
• ZX x Y
• Mlt0
• For in-1 to 0
• If Yi1, MltMX 2i
• ZltM

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Implementation Example
Multiply(X, Y, Z, start, done) Input X150,
Y150 type bit-vector, start type boolean
Local-Object A150, B150 ,M310,
i40 type bit-vector Output
Z310 type bit-vector, done type boolean S0
If start goto S0 S1 A lt X B lt Y ilt0
Mlt0 done lt 0 S2 If B15 0 goto S4
ilti1 S3 M lt MA S4 if igt 16, goto S6 S5
MltShift(M,L,1) BltShift(B,L,1) goto
S2 S6 Zlt M donelt 1 goto S0
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Implementation Example
Multiply(X, Y, Z, start, done) Input X150,
Y150 type bit-vector, start type boolean
Local-Object A150, B150, M310,
i40 type bit-vector Output
Z310 type bit-vector, done type boolean S0
If start goto S0 S1 A lt X B lt Y ilt0
Mlt0 done lt 0 S2 If B15 0 goto S4
ilti1 S3 M lt MA S4 if igt 16, goto S6 S5
MltShift(M,L,1) BltShift(B,L,1) goto
S2 S6 Zlt M donelt 1 goto S0
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ZXY
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Data Path Subsystem
operation A ? Load (X) B ? Load (Y) M?
Clear(M) i? Clear(i) i ? INC(i) M? Add(M,A) M ?
SHL(M) B ? SHL(B) Wires
control C0 C2 C4 C6 C7 C5 C1 C3
A lt X B ltY Mlt0 ilt0 ilti 1 MltMA MltShift(M,L
,1) BltShift(B,L,1) ZltM
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Data Path Subsystem
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Control Subsystem
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C0 C1 C2 C3 C4 C5 C6 C7 done
S0 0 0 0 0 0 0 0 0 1
S1 1 0 1 0 1 0 1 0 0
S2 0 0 0 0 0 0 0 1 0
S3 0 0 0 0 0 1 0 0 0
S4 0 0 0 0 0 0 0 0 0
S5 0 1 0 1 0 0 0 0 0
S6 0 0 0 0 0 0 0 0 1
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Control Subsystem
S6
S0
start
start
S1
S5
S2
i4
i4
B15
B15
S3
S4
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Summary

• Hardware Allocation
• Balance between cost and performance
• Resource Sharing and Binding
• Map operations to hardware
• Interconnect Synthesis
• Convey signal transports
• Operation Scheduling
• Sequence the process

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• Exercises
• Implement the control subsystem with one-hot
  state machine design.
• Try to reduce the latency of the whole system.