Synthesis for Test

1
Synthesis for Test

• Virendra Singh
• Indian Institute of Science
• Bangalore
• virendra_at_computer.org

IEP on Digital System Synthesis _at_ IIT Kanpur
2
Testability

• Objective
• Improve
• Controllability
• Observability
• Reduction in sequential depth
• Elimination of sequential loop

3
Sequential Depth Reduction - Allocation

• Allocation Scheme
• Enhance controllability and observability
• Reduction in Sequential depth
• Based on RT Architecture
• Independent of Test Technology

4
Controllability and Observability
a
Allocation 1 R1 a, c, g R2 b, d, h R3
e R4 f
b
c
d
e
f
g
h
Lifetime table
5
Controllability and Observability
a
Allocation 2 R1 a, c, R2 b, d R3 e,
f R4 f, g
b
c
d
e
f
g
h
Lifetime table
6
Controllability and Observability
If any one of variable assigned to a register is
a PI (PO) of the chip, this register is directly
controlled (observed) if not, register can be
accessed through other registers Goal To ensure
that as many registers as possible in the
implementation are assigned at least PI/PO Each
row of register must cover a PI/PO TSR1
Whenever possible , allocate a register to at
least one PI or PO
7
Sequential Depth Reduction
a
b
d
e
0
a
b
2
1
c
1
d
c
f
3
e
2
f
g
g
SDFG
Lifetime Table
8
Sequential Depth Reduction
TSR1 does not provide inform testability
suggestions on module allocation and interconnect
allocation Register allocation using TSR1 R
(a,c,g), (b,f), (d), (e) Two possible Module
allocation M1 (1,3), (2) M2 (1,2), (3)
9
Sequential Depth Reduction

• M1 is preferred to save interconnect cost
• output of 2 is hard to observe
• An error effect needs to propagate through an
  additional register R2 before it can be observed

10
Sequential Depth Reduction
d
a
b
R3
R (a,f,g), (b,c), (d), (e)
R1
R2
R4
g
e
TSR2 Reduce the sequential depth from an input
register to an output register
11
Sequential Depth Reduction
a
b
R (a,c,g), (b,f), (d), (e)
R1
R2
d
R3
g
R4
e
12
Sequential Loop Reduction
1
R1(a)
1
R2
2
R2(b)
2
R1
3
R3(c)
3
4
R3
R1(d)
Sequential Loop Reuse of R1
SDFG
13
Sequential Loop Reduction
x2
x9
x1
6
7
8
6
1
TIME 1
e
a
2
f
TIME 2
b
g
3
TIME 3
c
4
TIME 4
d
5
TIME 5
y
14
Sequential Loop Reduction
Alloc scheme Register Allocation Module allocation Mux loop FC
A1 R1 (x1,a), R2(x4,e,b) R3 (x6,f,c), R4(x7,d,g) R5 (x9,y) (1,4) (2,3) (3,7) (5,8) 19 3 84
A2 R1 (x6,e,b,c,d,y), R2(x1,a) R3 (x4,f), R4(x7,g) R5 (x9) (1,2) (6) (3,7) (4,5,8) 16 0 100
15
Sequential Loop Reduction
A1
R1
R4
R2
R3
R5
16
Sequential Loop Reduction
A2
R1
R4
R2
R3
R5
17
Scheduling for Sequential Depth/Loop Reduction
TSR3 Reduce Sequential loop by Proper resource
sharing to avoid creating sequential loops for
cyclic DFG Assign IO registers to break
sequential loop TSR4 Schedule operations to
support the application of TSR1, TSR2, and TSR3
18
Controllability
Primary input
a
Primary input
0
R(a)
0



R (b)
1
1
R(b)

-
-
2
R(c)
2
R(c)
R (b,c, ) Not directly controllable
R (a,b,c, ) Directly controllable
19
Observability
R2(z)
R1 (.,w,x, ) Not directly observable
20
Sequential Depth Reduction
t
R1(w)
R2(v)
2
1
t1
R3(s)
R1(x)
R2(y)
-
t2
R3(u)

t3
R2(z)
21
Mobility Path
1
2




6
8
10

TIME 1


7

lt
9
3
11
TIME 2
-
4
TIME 3
-
5
TIME 4
22
Mobility Path



TIME 1

-
TIME 2
-
TIME 3
TIME 4
23
Mobility Path Scheduling

• Mobility_path_scheduling(G)
• ASAP_scheduling(G)
• ALAP_scheduling(G)
• Update_op_slack_and_mobility(G)
• While (unscheduled_op(G) ? 0)
• Pk next_min_mobility_path(G)
• partial scheduling(Pk, G)
• testMP(Pk, G) /analyze testability on
  Pk

24
Mobility Path Scheduling

• partial_scheduling(Pk,G)
• For each (operation o on Pk)
• if (o.earliest o.latest) // mobility
  becomes 0
• o.active o.earliest // assign schedule
• Update_op_slack_and)mobility(G)
• While (unscheduled_op (Pk) ? 0)
• (o, o.ll_cycles) next_op_with
  _least_no_light_load_cycles(Pk, G)
• o.active most_preferred_cycle(o.ll_cycles
  , G)