LowFrequency Harmonic Reduction in SinglePhase Power Supply Systems

1
Low-Frequency Harmonic Reduction in Single-Phase
Power Supply Systems
Javier Sebastián
Universidad de Oviedo Spain
CIEP98-1
2
Focusing the presentation

• Ac-to-dc

• Single-Phase

Converter
Line

• Ac-to-ac

• Three-Phase

• Recovery to line

• High power

Energy
Power

• No recovery

• Low power
• (110-220V, lt16A)

• Modifying conv. topology

Philosophy

• External connection

CIEP98-2
3
Power Factor (PF) and Total Harmonic Distortion
(THD)
CIEP98-3
4
Questions (Q) Answers (A)

• Q Actually, are PF and THD the most important
  parameter from the point of view of regulations?
• A No, they are not
• Q What do regulations say about PF and THD?
• A Almost NOTHING. They only speak about the
  maximum value of each harmonic
• Q Frequently, what is the most usual objective
  designing?
• A To comply with regulations at as a low cost
  as possible. Neither PF1 nor THD0 are the main
  objectives

CIEP98-4
5
Suggestion to change words and concepts
Power Factor Correction
Low-Frequency Harmonic Reduction
Objectives

• To comply with regulations
• Low efficiency penalty
• Low cost penalty

CIEP98-5
6
IEC 1000-3-2
Class A
Balanced 3? equipment?
Yes
No
Class B
Portable tool?
Yes
No
igpeak
Class C
Lighting equipment?
35
Yes
?/3
?/3
?/3
No
Clase D Template
Especial Waveform Plt600 W?
Class D
Motor driven, ? control?
Yes
No
No
Yes
CIEP98-6
7
Special wave shape for Class D equipement
igpeak
Each half cycle of input current is within the
envelope for at least 95 of the time peak of
current coincides with center line
35
?/3
?/3
?/3
CIEP98-7
8
IEC 1000-3-2 Harmonics limits
CIEP98-8
9
Type of solutions
Input current waveform
sinusoidal
non-sinusoidal
passive non-sinusoidal
passive sinusoidal
passive
Devices
active sinusoidal
active non-sinusoidal
active
CIEP98-9
10
Passive solutions
Active solutions

• Preregulation
• Small size low weight
• No start-up problems
• Either low high power
• High quality of input current
• More expensive
• Less robust reliable

• Robust reliable
• Cost effective
• Low power
• No preregulation
• High weight big size
• Start-up problems
• Medium quality of input current

It depends on the input current goal
CIEP98-10
11
Sinusoidal input current
Non-sinusoidal input current

• Ideal operation
• Universal compliance
• High power
• Expensive
• Useless at 50-60Hz if passive
• Lower efficiency

• Higher efficiency
• Cheaper
• Either passive or active
• Compliance depending on regul.
• Low power

CIEP98-11
12
Type of solutions
Input current waveform
sinusoidal
non-sinusoidal
passive sinusoidal
passive non-sinusoidal
passive
Devices
active sinusoidal
active non-sinusoidal
active
CIEP98-12
13
Series-resonant tank
Useful at HF (e.g. 20 kHz)

• High PF, low THD
• Very bulky elements at 50-60Hz

IB
CR
LR
CB
VB
CIEP98-13
14
Design trade-off
Q Z/R
Voltage
Z(LR/CR)1/2
RVB/IB
Current

• The higher Q is
• The higher PF is
• The lower THD is
• The higher stresses in devices are
• The bulkier the inductor is

Low Q
Voltage
Current
High Q
CIEP98-14
15
Type of solutions
Input current waveform
sinusoidal
non-sinusoidal
passive non-sinusoidal
passive sinusoidal
passive
Devices
active sinusoidal
active non-sinusoidal
active
CIEP98-15
16
LC input filter with dc-side inductor (I)

• Up to 300W
• Design in Class D
• Different results if ac-side inductor

Either dc-to-ac or dc-to-dc converter
LF
CB
CIEP98-16
17
LC input filter with dc-side inductor (II)
200W, 180-260V
igpeak
23.3mH, EI-62.5, 0.58lb, 1.1W (losses)
35
200W, 90-260V
?/3
?/3
?/3
23.3mH, EI-87, 1.57lb, 2.74W (losses)
Current
CIEP98-17
18
LCC input filter with dc-side inductor
capacitor (I)

• Up to 300W
• Design in Class A
• Different results if ac-side inductor LF CF

Either dc-to-ac or dc-to-dc converter
LF
CF
CB
CIEP98-18
19
LCC input filter with dc-side inductor
capacitor (II)
Designing for Class A operation
igpeak
Class D template
35
?/3
?/3
?/3
Class D template
CIEP98-19
20
Type of solutions
Input current waveform
sinusoidal
non-sinusoidal
passive non-sinusoidal
passive sinusoidal
passive
Devices
active sinusoidal
active non-sinusoidal
active
CIEP98-20
21
Resistor Emulator concept
vg(?t)
VO
ig(?t)
IO
iO(?t)
IO
iO(?t)
ig(?t)
Resistor Emulator (dc-to-dc converter)
vg(?t)
VO
pg(?t)
pO(?t)
PO
CIEP98-21
PO
22
Resistor Emulators properties (I)
VO/ Vg
VO
VO??const.
m(?t)

vg(?t)
?sin(?t)?
vg(?t)
Resistor Emulator (dc-to-dc converter)
VO
vg(?t)

• The voltage conversion ratio m(?t) changes from
  VO/ Vg to infinity

CIEP98-22
PO
23
Resistor Emulators properties (II)
VO
IO
VO
R
r(?t)

iO(?t)
iO(?t)
2sin2(?t)
IO
iO(?t)
VO
RVO/IO

• The load resistance seen by the converter, r(?t),
  changes from R/2 to infinity

CIEP98-23
PO
24
Consequences of these properties (examples) (I)
ig
From property 1
VO
vg
??vg?
Buck working
VO
Buck off
??ig??
A Buck conv. cannot work as resistor emulator
CIEP98-24
25
Consequences of these properties (examples) (II)

• Series Resonant Converter (SRC) cannot be used as
  Resistor Emulator (from property 1)
• Zero-Voltage-Switched Quasi Resonant Converters
  (ZVS QRC) cannot be used as Resistor Emulator
  (from property 2), because they cannot operate
  at no load.

CIEP98-25
26
Consequences of these properties (examples)
(III)Study of the current conduction mode (I)
CIEP98-26
27
Consequences of these properties (examples)
(IV)Study of the current conduction mode (II)
kr(?t)gtkcritm(?t) CCM kr(?t)ltkcritm(?t)
DCM
kcritm(?t) kcritm(?t)/2sin2(?t)
Kapparent(R)2L/(RT)
Kapparent(R) gtkcritm(?t) CCM Kapparent(R)
ltkcritm(?t) DCM
CIEP98-27
28
Consequences of these properties (examples)
(V)Study of the current conduction mode (III)
Kapparent(R) gtkcritm(?t) CCM Kapparent(R)
ltkcritm(?t) DCM
max. of kcritm(?t) kcrit max
min. of kcritm(?t) kcrit min
ALWAYS CCM Kapparent(R) gt kcrit max ALWAYS
DCM Kapparent(R) lt kcrit min
CIEP98-28
29
Consequences of these properties (examples)
(VI)Study of the current conduction mode (IV)
vg(?t) Vg PEAK sin(?t)
MVO/Vg PEAK
CIEP98-29
30
Control of Resistor Emulators (I)
Multiplier approach control (I)
dc-to-dc converter
Input current fixed by the reference
CIEP98-30
31
Control of Resistor Emulators (I)
Multiplier approach control (II)
dc-to-dc converter
Input current sinusoidal its value fixed by the
reference
CIEP98-31
32
Control of Resistor Emulators (I)
Multiplier approach control (III)
Input current sinusoidal its value fixed by the
voltage feedback loop
CIEP98-32
33
Control of Resistor Emulators (II)
Voltage-follower approach control
dc-to-dc converter
Controller for dc-to-dc conv.
Low-pass filter
CIEP98-33
34

Control of Resistor Emulators (III)
Multiplier vs. Voltage-Follower
Multiplier
Voltage-Follower

• Either low or high output-impedance topologies
• Perfect PF THD
• Lower losses in the transistor
• Current sensor
• Multiplier
• More expensive

• No current sensor
• No multiplier
• Cheaper
• Lower losses in the diode
• Only high output-impedance topologies
• Sometimes THD

CIEP98-34
35
Control of Resistor Emulators (IV)
Improving THD in some converters with
voltage-follower control
CIEP98-35
36
Resistor emulator topologies (I)One switch, no
isolation (I)
Boost
Buck-boost
CIEP98-36
37
Resistor emulator topologies (II)One switch, no
isolation (II)
SEPIC
Cuk
CIEP98-37
38
Resistor emulator topologies (III)
Comparing basic topologies
CIEP98-38
39
Resistor emulator topologies (IV)

• One switch
• Isolation

Flyback
SEPIC
Cuk
CIEP98-39
40
Resistor emulator topologies (V)
Voltage-Follower control (I)
Buck-Boost in DCM
ig av
iL
iS
ig av
iL
iS
ig av
Ideal Resistor Emulator
CIEP98-40
41
Resistor emulator topologies (VI)
Voltage-Follower control (II)
ig av
Boost in DCM, fSconst.
iL
ig av
iL
ig av
Non-ideal Resistor Emulator
CIEP98-41
42
Resistor emulator topologies (VII)
Voltage-Follower control (III)
Boost in the boundary DCM/CCM
ig av
iL
iL
ton
toff

• ton const. each cycle
• toff depends on vg(?t)
• Therefore, fSvariable

CIEP98-42
43
Resistor emulator topologies (VIII)
Voltage-Follower control (IV)
iL
ig av
SEPIC Cuk in DCM
ig av
iL
ig av
Ideal Resistor Emulator (very low input current
ripple)
CIEP98-43
44
Resistor emulator topologies (IX)Two switches,
no isolation
Vg
VO
Buck
Boost
Vg
Boostoff Buckswt.
VO
Boostswt. Buckon
CIEP98-44
45
Resistor emulator topologies (X)Two switches,
isolation
To avoid starting-up stopping problems
Current-Fed Push-Pull
CIEP98-45
46
Resistor emulator topologies (XI)High-frequency
topologies (I)

• Integration of parasitics
• Only one switch
• Either ZCS or ZVS
• High output impedance (voltage-follower control)
• Higher stress (conduction losses)
• Frequency modulation

CIEP98-46
47
Resistor emulator topologies (XII)High-frequency
topologies (II) parasitic integration
LR
CR
CB
ZCS-QR SEPIC
CIEP98-47
48
Resistor emulator topologies (XIII)High-frequency
topologies (III) parasitic integration
PRC
CR
LR
Transformer Diodes Switches
CIEP98-48
49
Resistor emulator topologies (XIV)High-frequency
topologies (IV)voltage-follower control in
resonant converters
Voltage
Voltage
Current
Current
PRC
ZCS-QR SEPIC
CIEP98-49
50
Resistor emulator topologies (XV)High-frequency
topologies (V) Zero Voltage Transition topologies
Main diode
CD
LR
CR
CS
CB
Main switch
Aux. devices
ZVT Boost
CIEP98-50
51
Resistor emulator topologies (XVI)High-frequency
topologies (VI) Zero Voltage Transition in IGBT
using a MOSFET
CB
Saux
S1
S2
Main switches
Aux. switch
Current-fed Push-Pull
CIEP98-51
52
Dynamic problems in Resistor Emulators
With multiplier approach control
dc-to-dc converter
High gain at 100-120Hz
sin
10dB lower
20dB lower
Low-pass filter
Input current for different filters
Same case with Voltage-Follower
CIEP98-52
53
PFC based on an one-stage Resistor Emulator
voltage

• Cheap
• Efficient
• Poor dynamics
• Big bulk capacitor

Resis. Emul.
power
power
LOSSES
CIEP98-53
54
Fast-response topologies

• Two stages in cascade
• Two-stage integrated topologies

• Topologies with double power-processing
• Topologies with power processing lower than double

• Charge Pump or Line-Voltage Augmentation type
• Parallel PFCs
• Based on High-Efficient Post-Regulators

CIEP98-54
55
Two-stage PFC (I)
voltage
voltage

• Good dynamics
• Smaller bulk capacitor

Resis. Emul.
2nd S.

• Lower efficiency
• Expensive

power
LOSSES
LOSSES
In comparison with one-stage Resistor Emulators
CIEP98-55
56
Two-stage PFC (II)
Example
Resistor Emulator (Boost)
Dc-to-dc converter (Phase-Shifted Full Bridge)
CIEP98-56
57
Two-stage integrated topologies (I)
voltage

• Good dynamics
• Smaller bulk capacitor
• Cheaper

voltage
voltage

• High stress
• Low efficiency

Fast-PFC
Fast-PFC
LOSSES
CIEP98-57
58
Two-stage integrated topologies (II)
Dc-to-dc converter (Either DCM or CCM Flyback)
Resistor Emulator (DCM Boost)
CIEP98-58
59
Two-stage integrated topologies (III)
ig av

• DCM Boost Flyback
• If Flyback in DCM, lower voltage variation across
  CB
• Quasi-sinusoidal input current
• High voltage current stress in the transistor

ig av
CIEP98-59
60
Two-stage integrated topologies (IV)

• DCM SEPIC Flyback
• If Flyback in DCM, lower voltage variation across
  CB (even no variation)
• Sinusoidal input current
• High current stress in the transistor

CIEP98-60
61
Two-stage integrated topologies (V)
Boost Integrated with Flyback Rectifier/Energy
storage/Dc-to-dc converter (BIFRED)

• Almost the same as DCM Boost Flyback

CIEP98-61
62
Two-stage integrated topologies (VI)
Integrated Resistor Emulator inverter
Fluorescent Lamp

• DCM Boost Resistor Emulator Half-Bridge
  Parallel Resonant inverter

CIEP98-62
63
Charge Pump or Line-Voltage Augmentation type
topologies (I)

• Good dynamics
• Small bulk capacitor
• Higher efficiency

• Complex
• Double control (for perfect input current)

CIEP98-63
64
Charge Pump type topologies (II)
?VS(?t)
??ig(?t) ?
dc-to-dc or dc-to-ac converter
ig(?t)
?vS(?t)
?VB
??vg(?t) ?
CIEP98-64
65
Charge Pump type topologies (III)
Exampledouble Forward-Flyback
???ig(?t) ?
?vS(?t)
?VB

• vS(?t) operates in DCM
• vS(?t) controlled by FM

CIEP98-65
66
Charge Pump type topologies (IV)
ExampleFull-Bridge FM PRC
pg(?t)
?vS(?t)
pS(?t)
???ig(?t) ?
pS(?t)gt0.27pg(?t)
?vS(?t)
-

?VB/2
?VB/2
Full Bridge
FM PRC
CIEP98-66
67
Parallel PFC (PPFC) (I)
Power undergoing 2 transformations (32)
Input power
Output power
Power undergoing only 1 transformation (68)
CIEP98-67
68
Parallel PFC (PPFC) (II)

• Good efficiency

• Several Saux
• High stress Saux
• Difficult design and control

2nd stg.
Main stg.
68
CIEP98-68
69
PPFC (III) Example
CB
Forward
Current-fed Full Bridge
CIEP98-69
70
High-Efficient Post-Regulators Concept

• Two-Output One-stage PFC Two-Input Buck
  (TIBuck)
• Standard One-Stage PFC Series-Switching
  Post-Regulator (SSPR)

CIEP98-70
71
High-Efficient Post-Regulators (I)Two-Output
Resistor Emulator Two-Input Buck (TIBuck)
CIEP98-71
72
High-Efficient Post-Reg. (II) TIBuck
V1-V2
VO
VO
V1
V2
V2
VO-V2
V1-V2
V1-V2
VO-V2
V2
V2
V2
V2
V2IO undergoing no power processing, (VO-V2)IO
undergoing power processing
CIEP98-72
73
Computing TIBucks efficiency
is TIBuck efficiency
CIEP98-73
74
High-Efficient Post-Regulators (III)



Power processing in a PFC based on a TIBuck
PO1
P1
V1
VO
TIBuck
PO
R.Em.
PO2
85-90
P2
V2
LOSSES
?TB99-97
LOSSES
CIEP98-74
75
High-Efficient Post-Regulators (IV)Example
Two-output Flyback TIBuck
V162V
VO54V
V247V
-
PWM
R. Em.

TIBuck
LOW-PASS FILTER
-
PFC CONTROLLER

?85-82, vg85-264V rms
CIEP98-75
76
High-Efficient Post-Regulators (V)Series-Switchin
g Post-Regulator (I)
VOC
-

One-stage PFC (Resistor Emulator)


Isolated dc-to-dc converter
VO
VOSS
-
-
SSPR
(non-isolated )
VOCltlt VO
Pconv.ltltPPFC
CIEP98-76
77
Computing SSPR efficiency (I)
IO2
VOC
IO2
IO
-



IO1
Dc-to-dc converter ?C
VO
VOSS
-
-
SSPR ?ss
PWM
CIEP98-77
78
Computing SSPR efficiency (II)
Transient response
vOSS
vOC
Voltages
Steady state
vO
Time
CIEP98-78
79
High-Efficient Post-Regulators (VI)Series-Switchi
ng Post-Regulator (II)
Power processing
vOSS
vO
vOC
voltage
vO
DC/DC
R. Em.
85-90
SSPR
power
vOSS
LOSSES
LOSSES
?SSPR97-98
CIEP98-79
80
High-Efficient Post-Regulators (VII)Series-Switch
ing Post-Regulator (III)
Same type of converter
Dc-to-dc converter
Dc-to-dc converter
One-stage PFC
Dc-to-dc converter
n converters
Dc-to-dc converter
SSPR
Dc-to-dc converter
Dynamic response improves by using n1 converters
instead of n
CIEP98-80
81
High-Efficient Post-Regulators (VIII)Series-Switc
hing Post-Regulator (IV)
For discharging CB in short-circuit
Implementation based on a Forward converter
CIEP98-81
82
High-Efficient Post-Regulators (IX)Setting
voltages
83
Topologies based on TIBuck (I)
Current-Fed Push-Pull
TIBuck
CIEP98-83
84

Topologies based on TIBuck (II)
2xBoost
TIBuck
CIEP98-84
85
Topologies based on SSPR
CIEP98-85
86

PPFC versus 1 stg. PFC SSPR
Forward
Current-fed Full Bridge
Forward SSPR
Current-fed Full Bridge
CIEP98-86
87
PPFC versus 1 stg. PFC SSPR

• Smaller capacitor

power
power
2nd stg.
68
Main stg.
power
power
LOSSES
power
POSS
POC
DC/DC
Pd
POC
POSS
1-stg. PFC
85-90

• Higher
• Simpler control

SSPR
LOSSES
LOSSES
Pd
CIEP98-87
88
Type of solutions
Input current waveform
sinusoidal
non-sinusoidal
passive non-sinusoidal
passive sinusoidal
passive
Devices
active non-sinusoidal
active sinusoidal
active
CIEP98-88
89
Example Buck PFCOne switch, no isolation, slow
response
ig
VO
vg
Always VOltVg peak
vg
Buck working
VO

• No start-up problems
• Low stress in devices
• Slow transient response

Buck off
vg
vg
ig
ig
CIEP98-89
90
Objectives for many new converters
Small size ??Reactive elements at switching
frequency Cheap ??Only one transistor
controller Efficient ? Less than two power
conversions
CIEP98-90
91
Line-voltage augmentation based on an
additional output in dcm
Additional output in dcm
To help input rectifier to start conducting
Line
Load
Conventional dc-to-dc converter
Bulk cap.
CIEP98-91
92
Example I
Additional output in dcm
Bulk cap.
Filter cap.
Line
Flyback
Line
Bulk cap.
Load
INTELEC96
Filter cap.
CIEP98-92
93
Example II
Additional output in dcm
Line
INTELEC96
2 Switch Forward
CIEP98-93
94
Example III
DCM Flyback
CB
Forward with additional DCM Flyback-type output
CIEP98-94
95
Equivalent circuit with additional output in dcm
Characteristic
vO(is)
is
Non-linear Loss-Free Resistor
vO(is)
-

vLine
iLine
dc-to-dc standard converter
is
Bulk cap.
Load
Line

• Much energy re-cycled
• High current stress (dcm)
• Large variation in caps voltage

CIEP98-95
96
Desired equivalent circuit
Characteristic
vO(is)
is
Linear Loss-Free Resistor
vO(is)
-

is
vLine
iLine
dc-to-dc standard converter
Bulk cap.
Load
Line

• Less energy re-cycled
• Lower current stress (ccm)
• Smaller variation in caps voltage

CIEP98-96
97
How can it be implemented?Forward with LD and
with L in ccm
iL
iO
iLD
Driver
D1
LD
L
VO
Voltage across D2
D2
Vi
11 n
iL
iO
Characteristic
iLD

VOnVid - LDfSiO
vO(iO)

td
VS
VOVS - RLFiO
td/fS
iO
1/fS
VS/RLF
CIEP98-97
98
Circuit proposed this year (APEC98)
Forward with LD with L in ccm
LD
L
Line
Bulk cap.
Filter cap.
Flyback
L
LD
Load
Line
Bulk cap.
CIEP98-98
99
Active Input-Current Shaper (AICS)
VO(0)VS
vO(is)
is
n1
nS
n2
VS can be freely chosen
AICS
VS depends on the duty cycle
CIEP98-99
100
Generalization of the AICS concept
AICS
Forward converter (conventional)
AICS
Forward converter with active clamp
CIEP98-100
101
Designing the Active Input-Current Shaper
RLF
VS(Vg,PO)
vgVgsin?t
dc-to-dc converter
PO
VC(Vg,PO)
Vg min
VS min(Vg min , PO max)
VC(Vg,PO)
Vg max
RLF to minimize re-cycled energy
?C(Vg,PO)
PO max
CIEP98-101
102
Determining Class and compliance (IEC 1000-3-2)
Special wave shape
Class A ?Cgt86.3º compl. up to high power levels
(?1kW) Class D ?Clt86.3º compl. if ?Cgt67.4º
CIEP98-102
103
Design example 1
VS min Vg min d max0.66 Vg max1.2 Vg min
?C
VC/Vg
Input current
180º
3
Vgmin, Pmax
Vgmin
Vgmax, Pmax
Class A
120º
2
Vgmax
Vgmax
Vgmax, Pmax/2
boundary
Vgmin
1
60º
Class D
Vgmin, Pmax/2
0
0º
0
0 ?/3 2?/3 ?
0.5
1
0
0.5
1
Normalized power
Line angle
Normalized power

• High PF low THD
• High VC variation

CIEP98-103
104
Design example 2
VS min Vg min/2 d max0.66 Vg max1.4 Vg min
?C
VC/Vg
Input current
3
Class A
Vgmin
2
Vgmax
boundary
1
Vgmax
Vgmin
Class D
0
0
0.5
1
Line angle
Normalized power

• Lower VC variation
• Lower PF higher THD

CIEP98-104
105
Experimental results prototype
1.4mH
Line
430?H
Output
VC
Bulk cap.
Vg190V-250V VO50V, IO0.5-2A fS100kHz
CIEP98-105
106
Efficiency in the prototype
As dc-to-dc converter (voltage source across the
bulk capacitor)
As ac-to-dc converter with Input-Current
Wave-Shaping. ????3-7 points lower
CIEP98-106
107
Input current waveforms harmonics
CIEP98-107
108
Input current (transformer with extra tap)
CIEP98-108
109
AICS Conclusions

• Main conventional topologies (no extra switches)
• Only 2 additional inductors and 2 additional
  diodes
• High-frequency filtered input current (ccm)
• Low extra stress (ccm low capacitor voltage
  change)
• Main converter either in ccm or dcm
• Trade-off between harmonics and re-cycled energy
  (efficiency)
• Compliance with IEC 1000-3-2 with low efficiency
  penalty

CIEP98-109
110
Other types of shapers(I) (APEC97)
Either ccm or dcm. If ccm, leakage inductance is
needed
CIEP98-110
111
Other types of shapers(II) (Magnetic switch,
INTELEC95)
dcm
CIEP98-111
112
Conclusions

• Passive, non-sinusoidal solutions are very
  interesting for low-power applications.
• Topologies based on Resistor Emulators need
  topological transformations in order to improve
  dynamic response.
• Active, non-sinusoidal solutions are very
  interesting from the point of view of cost. This
  is a promising field for researching.

CIEP98-112