Moores Law

1
Moores Law
Electronics, April 19, 1965.
2
Evolution in Complexity
3
Transistor Counts
1 Billion Transistors
K
1,000,000
100,000
Pentium III
10,000
Pentium II
Pentium Pro
1,000
Pentium
i486
i386
100
80286
8086
10
Source Intel
1
1975
1980
1985
1990
1995
2000
2005
2010
Projected
Courtesy, Intel
4
Moores law in Microprocessors
1000
2X growth in 1.96 years!
100
10
P6
Pentium proc
Transistors (MT)
486
1
386
286
0.1
8086
Transistors on Lead Microprocessors double every
2 years
8085
0.01
8080
8008
4004
0.001
1970
1980
1990
2000
2010
Year
Courtesy, Intel
5
Die Size Growth
100
P6
Pentium proc
486
Die size (mm)
10
386
286
8080
8086
7 growth per year
8085
8008
2X growth in 10 years
4004
1
1970
1980
1990
2000
2010
Year
Die size grows by 14 to satisfy Moores Law
Courtesy, Intel
6
Frequency
10000
Doubles every2 years
1000
P6
100
Pentium proc
Frequency (Mhz)
486
386
10
8085
286
8086
8080
1
8008
4004
0.1
1970
1980
1990
2000
2010
Year
Lead Microprocessors frequency doubles every 2
years
Courtesy, Intel
7
Power Dissipation
100
P6
Pentium proc
10
486
286
8086
Power (Watts)
386
8085
1
8080
8008
4004
0.1
1971
1974
1978
1985
1992
2000
Year
Lead Microprocessors power continues to increase
Courtesy, Intel
8
Power will be a major problem
100000
18KW
5KW
10000
1.5KW
500W
1000
Pentium proc
Power (Watts)
100
286
486
8086
10
386
8085
8080
8008
1
4004
0.1
1971
1974
1978
1985
1992
2000
2004
2008
Year
Power delivery and dissipation will be prohibitive
Courtesy, Intel
9
Power density
10000
1000
Power Density (W/cm2)
100
8086
10
4004
P6
8008
Pentium proc
8085
386
286
486
8080
1
1970
1980
1990
2000
2010
Year
Power density too high to keep junctions at low
temp
Courtesy, Intel
10
Not Only Microprocessors
CellPhone
Digital Cellular Market (Phones Shipped)
(data from Texas Instruments)
11
Challenges in Digital Design
Macroscopic Issues Time-to-Market
Millions of Gates High-Level Abstractions
Reuse IP Portability Predictability
etc. and Theres a Lot of Them!

• Microscopic Problems
• Ultra-high speed design
• Interconnect
• Noise, Crosstalk
• Reliability, Manufacturability
• Power Dissipation
• Clock distribution.
• Everything Looks a Little Different

12
Productivity Trends
10,000,000
100,000,000
Logic Tr./Chip
1,000,000
10,000,000
Tr./Staff Month.
100,000
1,000,000
58/Yr. compounded
Complexity
10,000
100,000
Productivity (K) Trans./Staff - Mo.
Complexity growth rate
1,000
10,000
x
x
100
1,000
21/Yr. compound
x
x
x
x
x
Productivity growth rate
x
10
100
1
10
Source Sematech
Complexity outpaces design productivity
Courtesy, ITRS Roadmap
13
Why Scaling?

• Technology shrinks by 0.7/generation
• With every generation can integrate 2x more
  functions per chip chip cost does not increase
  significantly
• Cost of a function decreases by 2x
• But
• How to design chips with more and more functions?
• Design engineering population does not double
  every two years
• Hence, a need for more efficient design methods
• Exploit different levels of abstraction

14
Design Abstraction Levels
SYSTEM
MODULE

GATE
CIRCUIT
DEVICE
G
D
S
n
n
15
Design Metrics

• How to evaluate performance of a digital circuit
  (gate, block, )?
• Cost
• Reliability
• Scalability
• Speed (delay, operating frequency)
• Power dissipation
• Energy to perform a function

16
Cost of Integrated Circuits

• NRE (non-recurrent engineering) costs
• design time and effort, mask generation
• one-time cost factor
• Recurrent costs
• silicon processing, packaging, test
• proportional to volume
• proportional to chip area

17
NRE Cost is Increasing
18
Die Cost

• Single die

Wafer
Going up to 12 (30cm)
From http//www.amd.com
19
Cost per Transistor
cost -per-transistor
1
Fabrication capital cost per transistor (Moores
law)
0.1
0.01
0.001
0.0001
0.00001
0.000001
0.0000001
1982
1985
1988
1991
1994
1997
2000
2003
2006
2009
2012
20
Yield
21
Defects
a is approximately 3
22
Some Examples (1994)
23
Reliability?Noise in Digital Integrated Circuits
(
t
)
V
v
DD
i
(
t
)
Inductive coupling
Capacitive coupling
Power and ground
noise
24
DC OperationVoltage Transfer Characteristic
VOH f(VOL) VOL f(VOH) VM f(VM)
25
Mapping between analog and digital signals
V

1

OH
V
IH
Undefined
Region
V
IL

0

V
OL
26
Definition of Noise Margins
"1"
V
OH
Noise margin high
NM
H
V
IH
UndefinedRegion
V
NM
Noise margin low
L
IL
V
OL
"0"
Gate Input
Gate Output
27
Noise Budget

• Allocates gross noise margin to expected sources
  of noise
• Sources supply noise, cross talk, interference,
  offset
• Differentiate between fixed and proportional
  noise sources

28
Key Reliability Properties

• Absolute noise margin values are deceptive
• a floating node is more easily disturbed than a
  node driven by a low impedance (in terms of
  voltage)
• Noise immunity is the more important metric the
  capability to suppress noise sources
• Key metrics Noise transfer functions, Output
  impedance of the driver and input impedance of
  the receiver

29
Regenerative Property
Regenerative
Non-Regenerative
30
Regenerative Property
A chain of inverters
Simulated response
31
Fan-in and Fan-out
M
Fan-in M
32
The Ideal Gate
V
out
Fanout NMH NML VDD/2
g ?
V
in
33
An Old-time Inverter
5.0
NM
4.0
L
3.0
(V)
2.0
out
V
V
M
NM
H
1.0
0.0
1.0
2.0
3.0
4.0
5.0
V
(V)
in
34
Delay Definitions
35
Ring Oscillator
36
A First-Order RC Network
tp ln (2) t 0.69 RC
Important model matches delay of inverter
37
Power Dissipation
Instantaneous power p(t) v(t)i(t)
Vsupplyi(t) Peak power Ppeak
Vsupplyipeak Average power
38
Energy and Energy-Delay
Power-Delay Product (PDP) E Energy per
operation Pav ? tp
Energy-Delay Product (EDP) quality metric
of gate E ? tp
39
A First-Order RC Network
R
v
out
v
CL
in
40
Summary

• Digital integrated circuits have come a long way
  and still have quite some potential left for the
  coming decades
• Some interesting challenges ahead
• Getting a clear perspective on the challenges and
  potential solutions is the purpose of this book
• Understanding the design metrics that govern
  digital design is crucial
• Cost, reliability, speed, power and energy
  dissipation

41
The CMOS Inverter A First Glance
42
CMOS Inverter
N Well
PMOS
2l
Contacts
Out
In
Metal 1
Polysilicon
NMOS
GND
43
Two Inverters
Share power and ground Abut cells
Connect in Metal
44
CMOS InverterFirst-Order DC Analysis
VOL 0 VOH VDD VM f(Rn, Rp)
45
CMOS Inverter Transient Response
V
V
DD
DD
R
p
V
V
out
out
C
C
L
L
R
n
V
V
V
0
5
5
in
DD
in
(a) Low-to-high
(b) High-to-low
46
Voltage TransferCharacteristic
47
PMOS Load Lines
48
CMOS Inverter Load Characteristics
49
CMOS Inverter VTC
50
Switching Threshold as a function of Transistor
Ratio
51
Determining VIH and VIL
A simplified approach
52
Inverter Gain
53
Gain as a function of VDD
54
Simulated VTC
55
Impact of Process Variations
56
Propagation Delay
57
CMOS Inverter Propagation DelayApproach 1
58
CMOS Inverter Propagation DelayApproach 2
59
CMOS Inverters
1.2
m
m
2l
Out
In
GND
60
Transient Response
?
tp 0.69 CL (ReqnReqp)/2
tpHL
tpLH
61
Design for Performance

• Keep capacitances small
• Increase transistor sizes
• watch out for self-loading!
• Increase VDD (????)

62
Delay as a function of VDD
63
Device Sizing
(for fixed load)
Self-loading effect Intrinsic capacitances domina
te
64
NMOS/PMOS ratio
tpHL
tpLH
tp
b Wp/Wn
65
Impact of Rise Time on Delay
66
Inverter Sizing
67
Inverter Chain
In
Out
CL

• If CL is given
• How many stages are needed to minimize the
  delay?
• How to size the inverters?
• May need some additional constraints.

68
Inverter Delay

• Minimum length devices, L0.25mm
• Assume that for WP 2WN 2W
• same pull-up and pull-down currents
• approx. equal resistances RN RP
• approx. equal rise tpLH and fall tpHL delays
• Analyze as an RC network

2W
W
tpHL (ln 2) RNCL
tpLH (ln 2) RPCL
Delay (D)
Load for the next stage
69
Inverter with Load
Delay
RW
CL
RW
Load (CL)
tp k RWCL
k is a constant, equal to 0.69
Assumptions no load -gt zero delay
Wunit 1
70
Inverter with Load
CP 2Cunit
Delay
2W
W
Cint
CL
Load
CN Cunit
Delay kRW(Cint CL) kRWCint kRWCL kRW
Cint(1 CL /Cint) Delay (Internal) Delay
(Load)
71
Delay Formula
Cint gCgin with g ? 1 f CL/Cgin - effective
fanout R Runit/W Cint WCunit tp0
0.69RunitCunit
72
Apply to Inverter Chain
In
Out
CL
1
2
N
tp tp1 tp2 tpN
73
Optimal Tapering for Given N

• Delay equation has N - 1 unknowns, Cgin,2
  Cgin,N
• Minimize the delay, find N - 1 partial
  derivatives
• Result Cgin,j1/Cgin,j Cgin,j/Cgin,j-1
• Size of each stage is the geometric mean of two
  neighbors
• each stage has the same effective fanout
  (Cout/Cin)
• each stage has the same delay

74
Optimum Delay and Number of Stages
When each stage is sized by f and has same eff.
fanout f
Effective fanout of each stage
Minimum path delay
75
Example
In
Out
CL 8 C1
1
f
f2
C1
CL/C1 has to be evenly distributed across N 3
stages
76
Optimum Number of Stages
For a given load, CL and given input capacitance
Cin Find optimal sizing f
For g 0, f e, N lnF
77
Optimum Effective Fanout f
Optimum f for given process defined by g
fopt 3.6 for g1
78
Impact of Self-Loading on tp
No Self-Loading, g0
With Self-Loading g1
79
Normalized delay function of F
80
Buffer Design
N f tp 1 64 65 2 8 18 3 4 15 4 2.8 15.3
1
64
1
8
64
1
4
64
16
1
64
22.6
8
2.8
81
Power Dissipation
82
Where Does Power Go in CMOS?
83
Dynamic Power Dissipation
2
Energy/transition C
V
L
dd
2
Power Energy/transition
f
C
V

f
L
dd
Not a function of transistor sizes!
Need to reduce C
, V
, and
f
to reduce power.
L
dd
84
Modification for Circuits with Reduced Swing
85
Adiabatic Charging
2
2
2
86
Adiabatic Charging
87
Node Transition Activity and Power
88
Transistor Sizing for Minimum Energy

• Goal Minimize Energy of whole circuit
• Design parameters f and VDD
• tp ? tpref of circuit with f1 and VDD Vref

89
Transistor Sizing (2)

• Performance Constraint (g1)
• Energy for single Transition

90
Transistor Sizing (3)
VDDf(f)
E/Ereff(f)
F1
2
5
10
20
91
Short Circuit Currents
92
How to keep Short-Circuit Currents Low?
Short circuit current goes to zero if tfall gtgt
trise, but cant do this for cascade logic, so ...
93
Minimizing Short-Circuit Power
Vdd 3.3
Vdd 2.5
Vdd 1.5
94
Leakage
Sub-threshold current one of most compelling
issues in low-energy circuit design!
95
Reverse-Biased Diode Leakage
JS 10-100 pA/mm2 at 25 deg C for 0.25mm
CMOS JS doubles for every 9 deg C!
96
Subthreshold Leakage Component
97
Static Power Consumption
Wasted energy Should be avoided in almost all
cases, but could help reducing energy in others
(e.g. sense amps)
98
Principles for Power Reduction

• Prime choice Reduce voltage!
• Recent years have seen an acceleration in supply
  voltage reduction
• Design at very low voltages still open question
  (0.6 0.9 V by 2010!)
• Reduce switching activity
• Reduce physical capacitance
• Device Sizing for F20
• fopt(energy)3.53, fopt(performance)4.47

99
Impact ofTechnology Scaling
100
Goals of Technology Scaling

• Make things cheaper
• Want to sell more functions (transistors) per
  chip for the same money
• Build same products cheaper, sell the same part
  for less money
• Price of a transistor has to be reduced
• But also want to be faster, smaller, lower power

101
Technology Scaling

• Goals of scaling the dimensions by 30
• Reduce gate delay by 30 (increase operating
  frequency by 43)
• Double transistor density
• Reduce energy per transition by 65 (50 power
  savings _at_ 43 increase in frequency
• Die size used to increase by 14 per generation
• Technology generation spans 2-3 years

102
Technology Generations
103
Technology Evolution (2000 data)
International Technology Roadmap for
Semiconductors
Node years 2007/65nm, 2010/45nm, 2013/33nm,
2016/23nm
104
Technology Evolution (1999)
105
ITRS Technology Roadmap Acceleration Continues
106
Technology Scaling (1)
Minimum Feature Size
107
Technology Scaling (2)
Number of components per chip
108
Technology Scaling (3)
tp decreases by 13/year 50 every 5 years!
Propagation Delay
109
Technology Scaling (4)
From Kuroda
110
Technology Scaling Models
111

Scaling Relationships for Long Channel Devices
112
Transistor Scaling(velocity-saturated devices)
113
mProcessor Scaling
P.Gelsinger mProcessors for the New Millenium,
ISSCC 2001
114
mProcessor Power
P.Gelsinger mProcessors for the New Millenium,
ISSCC 2001
115
mProcessor Performance
P.Gelsinger mProcessors for the New Millenium,
ISSCC 2001
116
2010 Outlook

• Performance 2X/16 months
• 1 TIP (terra instructions/s)
• 30 GHz clock
• Size
• No of transistors 2 Billion
• Die 4040 mm
• Power
• 10kW!!
• Leakage 1/3 active Power

P.Gelsinger mProcessors for the New Millenium,
ISSCC 2001
117
Some interesting questions

• What will cause this model to break?
• When will it break?
• Will the model gradually slow down?
• Power and power density
• Leakage
• Process Variation