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IEEE P1801 Working Group (Unified Power Format

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Title: IEEE P1801 Working Group (Unified Power Format


1
IEEE P1801 Working Group(Unified Power Format
UPF)Status
  • Stephen Bailey
  • Chair, P1801 Working Group

2
Agenda
  • Quick Background
  • Key Technical Objectives of P1801
  • IEEE P1801 Schedule
  • QA

3
UPF Background
  • Initiated by users at DAC 2006
  • Accellera sponsorship Sep 2006
  • Donations from several companiesAtrenta, Magma,
    Mentor, Synopsys, TI
  • Accellera approves v1.0 of UPF Feb 2007
  • IEEE WG approved May 2007
  • UPF version 2.0

4
Key Objectives of P1801 (v2.0)
  • As with any 1.0 version, there are bugs and
    ambiguities
  • Discovered by vendors while implementing tool
    support
  • By users working through paper prototypes of
    how they would use UPF for their design needs
  • Enhancements to (better) address needs missed in
    v1.0

5
Highlights of P1801
  • Better support for soft IP incremental
    refinement of low power specification
  • Command layering for incremental specification
  • Allow multiple calls to same command with each
    call adding more, but not contradictory,
    information
  • Enhanced retention specification
  • Save and restore are functions defined in terms
    of one or more signals

6
Highlights of P1801 (2)
  • Enhanced power state information
  • Consistent with incremental refinement
  • Planned deferment of details (placeholders)
  • Can be specified prior to having a completed
    supply network specified for implementation
  • More information for verification and analysis as
    well as more complete information for optimizing
    implementation
  • Transitions as well as states
  • Defined access to state information from HDLs
  • Allows reference to states and triggering on
    state changes in TB within assertions

7
Support for Bias
  • Bias supplies
  • N-well, P-well, Deep-N-Well and Deep-P-Well
  • With defaults for each
  • New semantic definition corrupt-on-change
  • A power state can be attributed with this
    semantic specification
  • Represents a bias voltage threshold that has
    uncharacterized performance
  • Nets and registers retain current value
  • But are corrupted on any change while in this
    state
  • Emulates that switching will occur but with an
    unknown timing

8
Enhanced Semantic Specification
  • Improved semantic specification for
    set_related_power_pin(Name may change.)
  • Simulation semantics specified as well as
    implementation
  • When used on input, has semantic of a constraint
    for the source connected to the input
  • Merge power domains

9
P1801 Schedule
  • Weekly telecons (Tues mornings)
  • Except for weeks with F2F meetings
  • May begin 2nd set of weekly telecons to focus on
    technical issues to wrap-up
  • Monthly Face to Face Meetings
  • 15-17 Jan Magma hosted in SJ
  • 25-27 Feb Infineon hosted in Munich
  • 18-20 Mar Synopsys hosted in Mountain View
  • Draft standard for WG review
  • Feb 2008
  • Enter IEEE ballot
  • End of Mar 2008
  • Complete balloting May/June 2008

10
Contact Information
  • p1801_at_eda.org Email reflector
  • www.accellera.org/apps/org/workgroup/p1801
  • Chair stephen_bailey_at_mentor.com1 30 37 75 16
    55
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