KK4504 : Computer Architecture

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Computer Architecture

• Welcome to the KKK4504 class
• Dr. Abd Rahman Ramli
• Main Component of Lecture
• The Computer System
• The Central Processing Unit
• The Control Unit
• Advance Computer Design

Mail Text Book Computer Organization and
Architecture Designing for Performance,
By- William Stallings Prenrice Hall,
1996 Assessment Test 1 - 20, Test 2 -
20, Assignments - 30 Final Test - 30
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Distribution of Classes
1. Overview over Computer 2 2. System
Buses 4 3. Memories internal/external 6 4.
Input/output 2 5. Operating
System 2 6. Computer Architecture 8 7.
CPU structure and Function 5 8. RISC
instructions 4 9. High Performance Computer
(HPC) 3 10. Control Units 6 Date First
Test - / /98 Date Second Test -
/ /98
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Computer System

• What is computer system?
• The term computer is used to describe a device
  made
• up a combination of electronic and
  electromechanical (part
• electronic and part mechanical) components.
• By itself, a computer has no intelligence and is
  referred
• to as hardware. A computer system is a
  combination of five
• elements
• Hardware
• Software
• People
• Procedures
• Data/information

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Computer System
0101010 0101111 0001010

Hardware Software People Procedure
Data/ Information
Software is the term used to describe the
instructions that tell the hardware how to
perform a task without software
instructions, the hardware doesnt know what to
do. People constitute the most important of the
computer system. Procedure is the set of
instructions. The purpose of a computer system is
to convert data into information.
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Computer System
Computer hardware can be divided into four
categories 1. Input hardware. 2. Storage
hardware. 3. Processing hardware. 4. Output
hardware. The purpose of input hardware is to
collect data and convert it into a form suitable
for computer processing, keyboard, mouse, track
ball, digitizer, scanner ... The purpose of
storage hardware is to provide a means of
storing computer instructions and data in a form
that is permanent or nonvolatile - the data is
not lost when the power is turned off - and easy
to retrieve when needed for processing, hard
disk, tape drive, diskette, CD ...
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Computer System
The purpose of processing hardware is to
retrieve, interpret, and direct the execution of
software instruction provided to the
computer. The Central Processing Unit (CPU) is
composed of three units (1) the arithmetic-logic
unit (ALU) (2) main memory unit and (3) control
unit. ALU As its name indicates this unit takes
care of arithmetic operations (addition,
subtraction, multiplication and division) and
logic operations (such as comparing two numbers
to test for equality, or to test which is
greater). Main memory Main memory stores both
data and programs. They will be present in main
memory for only a relatively short time. Two
common types of memory used are RAM (Random
Access Memory) and ROM (Read-Only Memory).
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Computer System
Control unit The part of the CPU that control
the CPU and indirectly the entire computer
system. The control unit decides what to do next
and then directs it to be done. Output hardware
The purpose of output hardware is to provide the
user with the means to view information produced
by the computer system. Information is output
either hardcopy or softcopy form. Hardcopy output
can be held in your hand, such as paper with text
or graphics printed on it. Softcopy output is
displayed on a monitor, a television like screen
on which you can read text and graphics.
Control Unit
ALU
Main Memory Unit
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Computer System
Software is made up of a group of related
programs, each of which is a group of related
instructions that perform very specific
processing tasks. Software acquired to perform a
general business function is often referred to
as a software package. Software can generally be
divided into two categories (1) System
Software (2) Application Software. Programs
designed to allow the computer to manage its
own resources are called System software (Dos,
Windows, UNIX, OS) Any instructions or collection
of related programs design to be carried out by a
computer to satisfy a users specific needs are
Application software package.
WE THE PEOPLE
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Computer System
People operate the computer hardware they create
the computer software instructions and respond
to the procedures that those instructions
present. This processing includes refining,
summarizing, categorizing, and otherwise
manipulating data into a useful form for
decision making. Glossary CPU, ALU, RAM, ROM,
OS, DRAM, DPI, Control Unit, External Storage,
Hard/soft copy, Main Memory, Accumulator, Binary,
Chip, Decimal, Variable, application software
names (?). Go and get a leaflet from the
computer shop and find out all specifications.
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Computer System Software
Computer software contains the instructions or
commands that we want the computer to perform.
There are several important categories of
software, which include operating systems,
software tools, and language compilers.
USER
Application Software
Operating System
Hardware (PC, SUM etc.
( DOS, UNIX, WINDOWS, OS ..)
Software Interface to the computer
( Compilers, WP .. )
( Student, Eng... )
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Computer System Software
Operating System The operating system provides
an interface between you (the user) and the
hardware by providing a convenient and efficient
environment in which you can select and execute
the software on your system. Software
tool Software tools are programs that have
been written to perform common operations.
(Spreadsheet, computer-aided design, mathematical
computation tools, graphics tools..) Computer
Language Computer languages can be described
in terms of levels, Low-level and high-level
languages.
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Computer System Software
Low-level language Low-level languages,
machine languages or assembly languages are tied
closely to the design of the computer hardware.
Therefore machine language is a binary language,
and the instructions are written using two
symbols, which are usually represented using the
digit 0 and 1. High-level languages High-level
languages are computer languages that have
English like commands and instructions,
and include languages such as C, BASIC, JAVA,
FORTRAN, Pascal, COBOL, HTML, VRML.
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Computer System
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Communication lines
Computer System Software
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Computer System Software
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Computer System
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Memory Buffer Register (MBR) Contains a word to
be stored in memory, or is used to receive a word
from memory. Memory Address Register (MAR)
Specifies the address in memory of the word to be
written from or read into the MBR. Instruction
Register (IR) Contains the 8-bit op code
instruction being executed. Instruction Buffer
Register (IBR) Employed to temporarily hold the
instruction from a word in memory. Program
Counter (PC) Contains the address of the next
instruction-pair to be fetched from
memory. Accumulator (AC) and Multiplier-Quotient
(MQ) ...
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Problem (2.1) / Let A A(1),A(2),,A(1,000)
and B B(1),B(2),B(1,000) be two vectors (one-
dimensional arrays) comprising 1000 numbers each
that are to be added to form an array C such that
C(I) A(I)B(I) for I1,2,1000. Using the IAS
instruction set, write a program for this
problem. Answer / The vectors A,B, and C are each
stored in 1000 contiguous locations in memory,
beginning at locations 2000, 3000, and 4000,
respectively. The program begins with the left
half of location 3. ------------------------------
--------------------------------------------------
----------------------------- Location Instructi
on Comments -------------------------------------
--------------------------------------------------
---------------------- 0 - - 999 - Count
N 1 - - 1 - Constant 2 - - 1000 - Constant 3L
- - AC lt--- M(2000) - Transfer A(I) to
AC 3R - - AC lt--- AC M(300) Compute
A(I)B(I) 4L - - M(4000) lt--- AC Transfer sum to
C(I) 4R - - AC lt--- M(0) - Load count
N 5L - - AC lt---AC - M(1) - Decrement N by
1 5R - - IF AC ? 0 then go to M(6, 2039)
Test N 6L - - go to M(6, 019) - Halt 6R - - M(0)
lt--- AC - Update N 7L - - AC lt--- AC
M(1) - Increase AC by 1 7R - - AC lt--- AC
M(2) 8L - - M(3, 819) lt--- AC(2839) Modify
address in 3L 8R - - AC lt---AC M(2) 9L - - M(3,
819) lt--- AC(2839) Modify address in
3R 9R - - AC lt--- AC M(2) 10L - - M(4, 819)
lt--- AC(2839) Modify address in 4L 10R - - go to
M(3, 019) ---------------------------------------
--------------------------------------------------
-----------------------
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System Buses

• Three key concept of Von Neumann architecture
• Data and instructions are stored in a single
  read-write memory.
• The contents of this memory are addressable by
  location, without regard
• to the type of data contained there.
• Execution occurs in a sequential fashion (unless
  explicitly modified) from
• one instruction to the next.

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System Buses
CPU has two internal register a memory address
register (MAR), which specifies the address in
memory for the next read or write, and a
memory buffer register (MBR), which contains the
data to be written into memory or receives the
data read from memory.
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Computer Functions
CPU - Memory Data may be transferred from the
CPU to memory or from memory to CPU. CPU-I/O
Data may be transferred to or from the outside
world by transferring between the CPU and I/O
module. Data Processing The CPU may perform some
arithmetic or logic operation on data.
Instruction Format
Address
Op Code
0 3 4
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Integer Format
Magnitude
S
0 3 4
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Program Counter (PC) - Address of Instruction,
Instruction Register (IR) Instruction Being
Executed, Accumulator (AC) Temporary
Storage Internal CPU Registers (examples) 0001
Load AC from Memory 0010 Store AC to
Memory 0101 Add to AC from Memory
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Bus Interconnection
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Elements of Bus Design
Type Bus Width Dedicated Address
Multiplexed Data (control) Method
of Arbitration Data Transfer Type
Centralized Read Distributed
Write Read-modify-write Timing
Read-after-write Synchronous Block
Asynchronous
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Bus Types

• Two generic types
• Dedicated bus type The dedicated bus line is
  permanently assigned either to one function or to
  a physical subset of computer components. The
  advantage of physical dedication is high
  throughput, because there is less contention. A
  disadvantage is the increased size and cost of
  the system
• Multiplexed bus type Using the same line for
  address and data communication (Time
  multiplexing). The advantages of time
  multiplexing is the fewer lines, which save space
  and cost. The disadvantages are more complex
  circuitry and potential reduction of performance.

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Method of Bus Arbitration

• Basically two types
• In the concept of bus arbitration, a master (CPU
  or I/O module) will initiate a data transfer
  (e.g., read or write) to the other devices, and
  other part will acts as slave.
• Centralized method of bus arbitration scheme
  In a centralized scheme, a single hardware
  device, referred to as a bus controller or
  arbiter, is responsible for allocating time on
  the bus. The device may be a separate module or
  part of the CPU.
• Distributed method of bus arbitration In a
  distributed scheme, there is no central
  controller. Rather, each module contains access
  control logic and the modules act together to
  share the bus.

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Timing

• Timing refers to the way in which events are
  coordinated on the bus.
• Synchronous timing A clock will determine the
  coordination of the bus. There is a clock line in
  bus and all other devices on the bus can read the
  clock line, and all events start at the beginning
  of a clock cycle.
• Asynchronous timing In this timing, the
  occurrence of one event on a bus follows and
  depends on the occurrence of a previous event.
• Asynchronous timing is less flexible than
  asynchronous timing. The synchronous bus are tied
  to a fixed clock rate, the system cant take
  advantage of advances in device performance.
  Other hand, in asynchronous timing, a mixture of
  slow and fast devices, using older and newer
  technology, can share a bus.

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Bus Width and Data Transfer Type

• The width of Data bus has an impact on system
  performance.
• The width of address bus has an impact on system
  capacity

Read Write Read-modify-write Read-after-write Bloc
k
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Peripheral Component Interconnect (PCI) Bus System
PIC is designed for high-speed I/O subsystems
(e.g., graphic, display adapters, network
interface controllers, disk controller ..). 64
data line with 33 MHz data transfer rate is 264
Mbytes/sec, PIC has synchronous timing and a
centralized arbitration scheme.
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Peripheral Component Interconnect (PCI) Bus System
PIC is designed for high-speed I/O subsystems
(e.g., graphic, display adapters, network
interface controllers, disk controller ..). 64
data line with 33 MHz data transfer rate is 264
Mbytes/sec, PIC has synchronous timing and a
centralized arbitration scheme.
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Peripheral Component Interconnect (PCI) Bus System
PIC is designed for high-speed I/O subsystems
(e.g., graphic, display adapters, network
interface controllers, disk controller ..). 64
data line with 33 MHz data transfer rate is 264
Mbytes/sec, PIC has synchronous timing and a
centralized arbitration scheme.
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Peripheral Component Interconnect (PCI) Bus System

• System Pins Include the clock and reset pins
• Address and Data Pins Time-multiplexed for
  addresses and data.
• Interface Control Pines Control the timing of
  transactions.
• Arbitration Pines PCI master has its own pair
  of arbitration lines
• that connect it direst to the PCI bus arbiter.
• Error Reporting Pins Used to report parity and
  other errors.
• Interrupt Pins PCI device has its own interrupt
  line or lines
• to an interrupt controller.
• Cache Support Pines These pins support snoopy
  cache protocols.
• 64-bit Bus Extension Pines There are two lines
  that enable two
• PCI devices to the use of the 64-bit capability.
• JTAG/Boundary Scan Pines The signal lines
  support testing.

PCI Commands (Home work)
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PCI Data Transfers
Every data transfer on the PCI bus is a signal
transaction consisting of one address phase and
one or more data phases.
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PCI Bus Arbitration
PCI makes use of a centralized, synchronous
arbitration scheme in which each master has a
unique request (REQ) and grant (GNT) signal.
These signal lines are attached to a central
arbiter and a simple request-grant handshake is
used to grant access to the bus. It is a
first-come-first-served approach, a round-robin
approach, or some sort of priority scheme.
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PCI Bus Arbitration
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Assignment 1. Please put your comments over
the FUTUREBUS . Take note of every aspect of
BUS design. 2. (Q/3.13) Draw and explain a
timing diagram for a PCI write operations.
(3.3, 3.8, 3.10, 3.11, 3.12)
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Computer Memory System
Key characteristics of computer memory
systems Location Performance CPU Access
time Internal (main) Cycle time External
(secondary) Transfer rate Capacity Physical
Type Word size Semiconductor Number of
words Magnetic surface Unit of
Transfer Physical Characteristics Word Volatile/
non-volatile Block Erasable/non-erasable Access
Method Organization Sequential access Direct
access Random access Associative access
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The Memory Hierarchy
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Memory Chip
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Error Correction
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Cache Memory (the phenomenon of locality of
reference)
There is a relatively larger and slower main
memory together with a smaller, faster cache
memory. The cache contains a copy of portions of
main memory. Cache consists of C slots of K
works each, and the number of clots, or lines, in
considerably less than the number of main memory
block (C ltlt M). If a word in a block of memory is
read, that block is transferred to one of the
slots of the cache.
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Cache Memory Read Operation (the phenomenon of
locality of reference)
Elements of Cache Design Cache
Size Mapping Function Direct Associative
Set associative Replacement Algorithm
Least-recently used (LRU) First-in-first-out
(FIFO) Least-frequently used (LFU)
Random Write Policy Write Through Write back
Write once Block Size Number of Caches Single
or two-level Unified or split
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Mapping Function
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Associative Cache Mapping
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Associative Cache Mapping
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Associative Cache Mapping
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Associative Cache Mapping
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Pentium Processor
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Pentium Processor
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PowerPC
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PowerPC Cache State Diagram
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Enhanced Dynamic RAM (EDRAM)
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Synchronous Dynamic RAM (SDRAM)
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RamLink Architecture
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Magnetic Disk Data Layout
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Winchester Disk Track Format
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Characteristics of Disk Systems
Head Motion Platters Fixed head (one per
track) Single-platter Movable head (one per
surface) Multiple-platter Disk
Portability Head Mechanism Non-removable
disk Contact (floppy) Removable disk
Fixed gap Sides Aerodynamic gap
Single-sided (Winchester) Double-sided
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Multiple-Platter Disk
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Redundant Array of Independent Disks (RAID)
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Optical Memory Compact Disk (CD)
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I/O Modules
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I/O Modules

• I/O Module Functions
• Control and Timing to coordinate the flow of
  traffic between internal resources and external
  devices. (1) The CPU interrogates the I/O module
  to check the status of the attached device. (2)
  The I/O module returns the device status. (3) If
  the device is operational and ready to transmit,
  the CPU requests the transfer of data, by means
  of a command to the I/O module. (4) The I/O
  module obtains a unit of data from the external
  device. (5) The data are transferred from the I/O
  module to the CPU.
• CPU Communication to communicate with the CPU
  and the external devices. (1) Command decoding,
  (2) Data, (3) Status reporting (4) Address
  Recognition
• Device Communication
• Data Buffering
• Error Detection

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Programmed I/O, Interrupt-Driven I/O and Direct
Memory Access
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Memory-mapped and isolated I/O
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Memory-mapped and isolated I/O
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Memory and register for an interrupt
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Interrupt Controller (8259A)
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Interrupt Controller (8259A)
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Keyboard/Display Interface to 8255A
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Direct Memory Access
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Input/Output Channels
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External Interface
Parallel and Serial Interface Point-to-Point and
Multi-point Configuration Small Computer System
Interface (ACSI)
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SCSI Bus Signals
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SCSI Bus Timing Diagram
Bus Free Delay Bus Set Delay
Bus Settle Delay
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SCSI Command
8 bits

• The execution of the command
• involves some or all of the following
• steps
• The target acquires and decodes command
  information.
• Data is transferred to or from the target not
  performed for all commands
• The target generates and returns status
  information.
• SCSI-2 standard includes commands for the
  following device types
• direct-access devices, sequential-access device,
  printers, processors, write-one device, CD-ROMs,
  scanners, optical memory devices, medium-changer
  devices, communication devices.

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P1394 Serial Bus and SCSI Bus
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P1394 Configuration
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P1394 Configuration
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Operating System
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Operating System
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Multiprogramming
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Uniprogramming vs. Multiprogramming Histogram
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Scheduling
Multiprogramming High-level Scheduling The
high-level scheduler determines which programs
are admitted to the system for processing.
(degree of multiprogramming- number of processing
in memory). In a batch system, newly submitted
jobs are routed to disk and held in a queue or
waiting line. In time sharing, a process request
is generated by the act of a user attempting to
connect to the system. Time-sharing users are not
simply queued up and kept waiting until the
system can accept them. Rather, the operating
system will accept all authorized comers until
the system is saturated. At that point, a
connection request is met with a message
indicating that the system is full and the user
should try again later. Short-Term Scheduling
Known as the dispatcher, executes frequently and
makes the fine-grained decision of which job to
execute next. Process state concept - New,
Ready, Running, Waiting, Halted.
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Scheduling Techniques
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Memory Management and Partitioning
Variable-size partitions Compaction
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Paging or page frames
Virtual Memory
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Page Table Structure
Translation Lookaside Buffer
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Segmentation
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Segmentation
The advantages are 1. It simplifies the handling
of growing data structures. 2. It allows programs
to be altered and recompiled independently. 3. It
lends itself to sharing among processes. 4. It
lends itself to protection.
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Pentium Memory Management
Address Spaces Unsegmented Unpaged Memory,
Unsegmented paged Memory, Segmented
Unpaged memory, segmented paged
memory. Segmentation The physical address space
employs a 32-bit address for a maximum of 4
Gbytes. Unsegmented memory, the users virtual
memory is 232 4 Gbytes. With segmented memory,
the total virtual memory space as seen by a user
is 246 64 terabytes (Tbytes).
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Pentium Memory Management (Memory address
translation mechanisms) and PowerPC
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PowerPC Memory Management
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Problems
Q/7.2/ The answers are the same for (a) and (b).
Assume that although CPU operations
cannot overlap, I/O operations can. 1 Job TAT
NT CPU utilization 50 2 Job TAT NT CPU
utilization 100 4 Job TAT (2N - 1)T CPU
utilization 100 Q/7.7/ With very small
page size, there are two problems (1) Since very
little data is brought in with each page, there
will need to be a lot of I/O to bring in the many
small pages. (2) The overhead (page table size,
length of field for page number) will be
disproportionately high. If pages are very
large, main memory will be wasted because the
principle of locality suggests that only a small
part of the large page will be used.
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The Central Processing Unit (CPU)
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CPU
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CPU
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Instruction Sets Characteristics and Functions
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Instruction Sets Characteristics and Functions
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Instruction Sets Characteristics and Functions
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Instruction Sets Characteristics and Functions
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Instruction Sets Addressing Modes and Formats
Mode Algorithm Principal Advantage Principal
Disadvantage -------------------------------------
--------------------------------------------------
---- Immediate Operand A No memory
reference Limited Operand magnitude Direct EAA Si
mple Limited address space Indirect EA(A) Large
address space Multiple memory references Register
EAR No memory reference Limited address
space Register indirect EA(R) Flexibility Comple
x Stack EAtop of stack No memory reference
Limited applicability
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Addressing Modes
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Instruction Format

• Instruction Length
• Allocation of Bits
• Number of Addressing Modes
• Number of Operands
• Register vs. Memory
• Number of Register sets
• Address Range
• Address Granularity

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Pentium Instruction Format
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CPU Structure and Function
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The Instruction Cycle
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Data Flow
Instruction Pipelining
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Instruction Pipelining
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Instruction Pipelining
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Instruction Pipelining
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Reduced Instruction Set Computers RISC

• The major advances are The Family Concept,
  Micro-programmed Control, Cache Memory,
  Pipelining, Multiple Processors.
• RISC System
• A limited and simple instruction set.
• A large number of general-purpose registers, or
  the use of compiler technology to optimize
  register usage.
• An emphasis on optimizing the instruction
  pipeline.

CISC - Complex Instruction Set Computer
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RISC - Instruction Execution Characteristics

• The goal
• Ease the task of the compiler writer.
• Improve execution efficiency.
• Provide support for even more complex and
  sophisticated high-level language.
• The aspects of computation of interest are
• Operations Performed These determine the
  functions to be performed by the CPU and its
  interaction with memory.
• Operands Used The types of operands and the
  frequency of their use determine the memory
  organization for storing them and the addressing
  modes for accessing them.
• Execution Sequencing This determines the
  control and pipeline organization.
• Operations, Operands,
  Procedure Calls and Implication

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RISC - Instruction Execution Characteristics
Large Register File This is intended to optimize
operand referencing. Local registers are used
for local variables, as assigned by the compiler.
Temporary register are used to exchange
parameters and results with the next lower level.
Current-window pointer (CWP) is used.
Global Variable 1. Variables declared as global
in an HLL can be assigned memory locations by the
compiler and all machine instructions that
reference these variables will use memory
reference operands. 2. Alternative is to
incorporate a set of global registers in the CPU.
May be with unified numbering scheme.
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RISC - Instruction Execution Characteristics
Large Register File Versus Cache
Register File The
register file, organized into windows, acts as a
small, fast buffer for holding a subset of all
variables that are likely to be used the most
heavily. The window-based register file holds all
local scalar variables. The register file should
save time, since all local scalar variables are
retained. The register file contains only
variables those are in use. A register file may
make inefficient use of space, since not all
procedures will need the full window space
allotted to them. With the register file, the
movement of data between register and memory is
determined by the procedure nesting depth.
Cache Memory The
register file acts much like a cache memory. The
cache holds a selection of recently used scalar
variables. The cache may make more efficient use
of space, since it is reacting to the situation
dynamically. The cache is capable of handling
global as well as local variables. The cache
reads in a block of data, some or much of which
will not be used. Most cache memories are set
associative with a small set size. Thus, there is
the danger that other data or instructions will
overwrite frequently used variables.
The register approach is clearly superior and
which suggests that a cache-based system will be
noticeably slower.
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RISC - Instruction Execution Characteristics
Compiler-based Register
Optimization The objective of the compiler is to
keep the operands for as many computations as
possible in registers rather than main memory,
and to minimize load-and-store operations. Each
program quantity that is a candidate for residing
in a register is assigned to a symbolic or
virtual register. The compiler then maps the
unlimited number of symbolic register into a
fixed number of real registers. Symbolic
registers whose usage does not overlap can share
the same real register. If, in a particular
portion of the program, there are more quantities
to deal with than real registers, then some of
the quantities are assigned to memory locations.
Load-and-store instructions are used to
temporarily position quantities in registers for
computational operations.
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RISC - Architecture
CISC Desire to simplify compilers and a desire
to improve performance RISC Program takes up
less memory. Fewer instruction means fewer
instruction bytes to be fetched. In a paging
environment, smaller programs occupy fewer pages,
reducing page faults.
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Characteristics of RISC Architecture
CISC Versus RISC Characteristics
1. A simple instruction size. 2. That size is
typically 4 bytes. 3. A small number of data
addressing modes, typically less than five. 4. No
indirect addressing mode. 5. No operations that
combine load/store with arithmetic. 6. No more
than one memory-addressed operand per
instruction. 7. Does not support arbitrary
alignment of data for load/store operations. 8.
Maximum number of uses of the memory management
unit (MMU) for a data address in an instruction.
9. Number of bits for integer register specifier
equal to five or more. 10. Number of bits for
floating-point register specifier equal to four
or more. 1-3 (instruction decode complexity) 4-8
(difficulty of pipelining) and 9-10 (good
advantage of compilers).
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RISC Pipelining

• Most instructions are register-to-register, and
  an instruction cycle has the following two
  phases
• I Instruction Fetch.
• E Execute. Performs an ALU operation with
  register input and output.
• For load and store operations, three phases are
  required
• I Instruction Fetch.
• E Execute. Calculates memory address.
• D Memory. Register-to-memory or
  memory-to-register operation.

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RISC Pipelining
Optimization of Pipelining
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Motorola 88000 - Instruction Set
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Motorola 88000 - Instruction Set
Architecture The main processor chip consists of
multiple independent function units connected to
a multiported register file. The function units
can operate independently and concurrently, provid
ing a very efficient means of processing
instructions. (1) Integer Unit, (2)
Floating-Point Unit, (3) Instruction Unit, (4)
Data Memory Unit. The memory bus interface two
cache memory management units to the memory
system, one for data and one for instructions.
This feature is implemented on a number of recent
RISC system. Register Management It has 32 bit
32 general purpose registers. Instruction Unit
Pipeline
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Motorola 88000 - Instruction Set
The RISC versus CISC controversy The RISC
approach can be grouped into two categories (1)
Quantitative, (2) Qualitative. Most commercially
available machines advertised as RISC a mixture
of RISC and CISC characteristics. (80X86)
Function Units
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The RISC versus CISC
Kiviat graph is used to assess the degree to
which a processor exhibits RISC characteristics.
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The RISC versus CISC
Kiviat graph is used to assess the degree to
which a processor exhibits RISC characteristics.
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Superscalar Processors
A superscalar implementation of a processor
architecture is one in which common instructions
- integer and floating-point arithmetic, loads,
stores, and conditional branches- can be
initiated simultaneously and executed
independently.

• The superscalar approach depends on the ability
• to execute multiple instructions in parallel. A
• combination of compiler-based optimization and
• hardware techniques can be used to maximize
• instruction-level parallelism.
• True Data Dependency
• Procedural Dependency
• Resource Conflicts
• Output Dependency
• Antidependency

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Superscalar Processors

• True Data Dependency
• Procedural Dependency
• Resource Conflicts
• Output Dependency
• Antidependency

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