Verilog Simulation with SYNAPTICAD Tool

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Verilog Simulation with SYNAPTICAD Tool

• ???
• 95/10/31

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Tool Installation
Click to install
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Execution of The Tool
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Interface of The Tool
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Add a New File (1/3)
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Add a New File (2/3)

• Enter the Examples directory

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Add a New File (3/3)

• Take the file add4.v as an example

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Compile The File (1/2)
Compile the file
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Compile The File (2/2)
Compile Complete
Simulation Waveform
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Simulation with Manual Stimuli (1/5)
Ungroup the signal
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Simulation with Manual Stimuli (2/5)
Press ??
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Simulation with Manual Stimuli (3/5)
Select High or Low
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Simulation with Manual Stimuli (4/5)
Group the signal
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Simulation with Manual Stimuli (5/5)
Complete the simulation
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Simulation with a Testbench (1/5)
Add the testbench file
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Simulation with a Testbench (2/5)
Take the file add4test.v as an example
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Simulation with a Testbench (3/5)
Simulate the testbench
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Simulation with a Testbench (4/5)
Complete the simulation
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Simulation with a Testbench (5/5)
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Verilog Syntax (1/2)
Module name
IO list
module fulladder (sum, c_out, x, y, c_in)
output sum, c_out // Output port input x, y,
c_in // Input port wire a, b, c
// Internal wire xor (a, x, y) xor (sum,
a, c_in) and (b, x, y) and (c, a,
c_in) or (c_out, c, b) endmodule
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Verilog Syntax (2/2)
module FourBitAdder(sum, c_out, x, y, c_in)
output 30 sum output c_out input 30
x, y input c_in wire c1, c2, c3
fulladder fa0 (sum0, c1, x0, y0, c_in)
fulladder fa1 (sum1, c2, x1, y1, c1)
fulladder fa2 (sum2, c3, x2, y2, c2)
fulladder fa3 (sum3, c_out, x3, y3,
c3) endmodule
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Homework Assignment 2

• module FourBit_Comparator (Z1, Z2, A, B)
• Input 30 A,B
• output Z1, Z2
• endmodule