AN OVERVIEW OF SIGMA-DELTA CONVERTERS

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AN OVERVIEW OF SIGMA-DELTA CONVERTERS
G. S. VISWESWARAN PROFESSOR ELECTRICAL
ENGINEERING DEPARTMENT INDIAN INSTITUTE OF
TECHNOLOGY, DELHI NEW DELHI 110 016 Email
gswaran_at_ee.iitd.ac.in Telephone [phone]
[phone]
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DOMAIN OF CONVERTERS
Sigma Delta
Successive Approx
Subranging/Pipelined
Flash
Signal bandwidth converted
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PCM NYQUIST RATE A/D CONVERTERS
En is a sample sequence of a random process
uncorrelated with the sequence xn. The
probability density of the error process is
uniform over the range of quantization error i.e
over ??/2 The error is a white noise process
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PCM NYQUIST RATE A/D CONVERTERS
The variance of the noise power for a
quantization level ? is given by
This gives us an SNR
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PCM NYQUIST RATE A/D CONVERTERS
In a Nyquist converter, the maximum signal to
noise ratio that can be obtained for a sinusoidal
input with a peak voltage of V is given
by     ? Every additional bit ? 6dB of
SNR.   eg. Digital audio with signal bandwidth
20kHz. If desired resolution 18 bits
? SNR ? 110dB.
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PCM NYQUIST RATE A/D CONVERTERS
What is the problem with getting 18 bits of
resolution ?   1.      Nyquist rate converters
essentially obtain output by comparing the input
voltage to various reference levels. These
reference levels are obtained by a process of
reference division using resistors or
capacitors. Any mismatch in the
resistors/capacitors results in loss of
accuracy. 2.    For an N bit converter, the
required matching of elements is at least 1 part
in 2N. Matching of components to gt 10 bits (or gt
0.1 ) is difficult. 3.   Nyquist rate converters
require a sharp cutoff anti-aliasing filter.
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OVERSAMPLED PCM CONVERTERS
Oversampled converters attempt to use relatively
imprecise analog components with additional
digital signal processing circuits to achieve
high resolution. This is done using
 ? Oversampling - the sampling frequency is
much higher than the signal frequency
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OVERSAMPLED PCM CONVERTERS
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OVERSAMPLED PCM CONVERTERS
Noise spectrum when sampled at fS gtgt
2fB   ? Assume quantization noise is uniformly
distributed, white and uncorrelated with the
signal. ? Noise power folds back to fS/2 to
fS/2, ? oversampled converters have lower noise
power within the signal band. ? Out of band noise
can be removed by a digital filter following the
PCM converter.
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OVERSAMPLED PCM CONVERTERS
We define Power Spectral Density of the output
random Process is given by
For an oversampled PCM converter Hx(f)
He(f) 1. White noise assumption states that
Pe(f) Se2(f)/fs which implies Pey(f)
Sey2(f)/fs. Thus the in band noise power is given
by
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OVERSAMPLED PCM CONVERTERS
We now see that the SNR ratio for this converter
is
The spectrum of the (over) sampled signal can
represented as follows
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OVERSAMPLED PCM CONVERTERS
? 16-bit resolution digital audio Oversampled
8-bit converter to be used. To get an SNR
110dB with fB 20kHz, we need fS ? 2.64GHz. This
is still not good enough since the sampling
frequency is too high. Further improvement can be
obtained if noise shaping is used.
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NOISE SHAPED OVERSAMPLED PCM CONVERTERS
We see that for an A/D converter the output is
given in general by Y(z) X(z)Hx(z)
E(z)He(z) We have seen OS PCM converter using
Hx(z) He(z) 1. We can however realize
another converter using Hx(z) 1 but choose
He(z) to shape the noise spectrum to improve the
noise performance. Noise shaping or modulation
further attenuates noise in the signal band to
other frequencies. The modulator output can be
low pass filtered to attenuate the out of band
noise and finally down sampled to get Nyquist
rate samples.
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OVERSAMPLED NOISE SHAPING
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NOISE SHAPED OVERSAMPLED PCM CONVERTERS
? Noise is high pass filtered to get additional
resolution ? Simplest z- domain high pass filter
1 z-1 ?We want an output Y(z) that contains the
sun of the input and quantzation noise that is
high pass filtered. i.e. Y(z) X(z)
(1-z-1)E(z) or z-1X(z)
(1- z-1)E(z)
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NOISE SHAPED OVERSAMPLED PCM CONVERTERS
Digital
Analog
One possibility is to first integrate the analog
input, quantize it and then high pass filter it.
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FIRST ORDER ?? MODULATION
The naïve system proposed has its own problems.
The first problem is that since it is an open
loop system, the integrator will saturate. It
also requires matching between analog and digital
portions of the circuit.
Y(z) z-1X(z) (1 z-1) E(z)
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FIRST ORDER ?? MODULATION
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FIRST ORDER ?? MODULATION
 Linearized z domain model gives   Hx(z) STF
z-1 He(z) NTF 1-z-1  Assuming that the
quantization noise is uncorrelated with the
signal,   Sxy(f) Sx(f)?Hx(f) ?2 Sey(f)
Se(f)?He(f) ?2
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FIRST ORDER ?? MODULATION
If fBltlt fS
Thus we obtain the Noise Power as
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Taking OSR to be of the form 2r we can obtain the
SNR as
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FIRST ORDER ?? MODULATION
Noise power coming out of First Order Modulator
for an OSR of 128.
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FIRST ORDER ?? MODULATION
Before we proceed to implement the transfer
function we need to look in to certain
realizatios in the sampled data domain. As the
word ?? implies there is an integration involved.
In the continuous domain, this requires
resistance and capacitance. As a designer we
have the Capacity to Design but not the
Resistance.
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SWITCHED CAPACITOR CIRCUITS DOYEN OF SAMPLED DATA
DESIGNS
Sampled Signals
This gives a z transform
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Realizing resistors for Sampled Data Circuits
i1
i2
The average value of current i1 or i2 is given by
This emulates a resistance of value R T/C 1/fC
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OTHER REALIZATIONS OF R
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SWITCHED CAP INTEGRATORS
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SWITCHED CAP INTEGRATORS
During ?1
During ?2
Using z transforms, this reduces to
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SWITCHED CAP INTEGRATORS
If ? ltlt 1/T, and using z exp(j?T) we get
H(ej?T) as
This circuit is then an integrator with a delay
using the transformation s (z-1)/T and is
called the Forward Euler Integrator.
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SWITCHED CAP INTEGRATORS
This is another integrator that gives a non
inverting integration at the output and uses the
transformation s (1-z-1)/T and is called the
Backward Euler Integrator.
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SWITCHED CAP INTEGRATORS
The sampling capacitor Cs is now effectively Cs
CP, thus making the realized resistance R T/(Cs
CP), different from the intended value ---
needs correction, look for parasitic insensitive
configuration.
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SWITCHED CAP INTEGRATORS
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SWITCHED CAP INTEGRATORS
At ?1 Cs gets charged to Vin(nT) and During ?2
Giving us
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SWITCHED CAP INTEGRATORS
This configuration gives
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BACK TO SIGMA DELTA CONVERTERS
Implementation Imperfection in the first order
sigma-delta modulator            Finite op-amp
gain          Capacitance mismatch         
Incomplete settling
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FINITE OPAMP GAIN
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FINITE OPAMP GAIN
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FINITE OPAMP GAIN
Using charge conservations at the nth clock
cycle, we have CSVIn- CSVdn CF Von
Vdn Von-1 - Vdn-1
Using Von Avdn and writing in z domain
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FINITE OPAMP GAIN
?Output of the modulator is now given by
where NTF denotes the noise transfer function and
STF denotes the signal transfer function,  ?NTF
0 is shifted away from DC. Neglecting the
effect of the pole in the NTF,
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FINITE OPAMP GAIN
1 ?2-2? cos ?
For small ?
? Noise power at the output is then
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FINITE OPAMP GAIN
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EFFECT OF FINITE BANDWIDTH
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EFFECT OF FINITE BANDWIDTH
Larger feedback factor ? lower gain ? faster
setting
Settling determines maximum clock frequency eg
CS CF 1pF ? ? 0.5 Assume ?u 100 MHz If
we want setting to 1 error, time required ?
14.6ns ? clock frequency 34MHz.
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TIME DOMAIN BEHAVIOUR
  Yn Y n-1 (Xn-1 Vn-1) if Yn ?
0 Yn 1.0 else Yn - 1.0
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TIME DOMAIN BEHAVIOUR
For example, for a DC input , the time domain
output for the first six clock cycles is given by
It can be seen that the average value of the
output is 1/3
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TIME DOMAIN BEHAVIOUR (Non Linear)
 Quantization error spectrum is not white
successive output levels may be
correlated.   Limit cycle oscillations that lead
to tones in the output eg. DC input Xn x  For
a limit cycle of period T Vn
VnT ? Yn YnT Since the input is DC,
the input to the integrator will also be periodic.
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TIME DOMAIN BEHAVIOUR (Non Linear)
Now Yn Yn-1 X Vn-1. Write this
equation for T time instances and add we get
but YT Y 0
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PATTERN NOISE IN ?? MODULATOR
It should be clear that the ?? MODULATOR is
expected to give out the output equal to the DC
input. Only limited no. of levels are allowed to
the output , therefore output has to toggle from
one level to another in order to keep average
output equal to the DC input. For eg.
Input0.5 Levels allowed are 0 and 1 Then the
output will toggle between 0 and 1. If average is
taken then the value of output of SDM is
0.5. Therefore the output is oscillating with a
frequency half of that of fs. That means in
frequency domain the output will have tones at
fs/2 and fs.
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PATTERN NOISE IN ?? MODULATOR
Similarly for dc level of 1/256, the output will
have, one one and 255 zeroes in 256 clocks (fs)
this means the output will oscillate at a
frequency of (fs/256). Hence it will have tones
lying at multiples of this frequency. As the dc
level comes closer to zero the tonal frequency
decreases. The tones are completely harmless till
they are out of the signal bandwidth. The thing
to note over here is that these tones represent
noise as the information or signal is at 0
frequency rest of the frequency components are
noise. This effect is very much prominent in I
order modulators. Another important fact is that
the amplitudes of the tones decrease as they come
closer to the signal bandwidth. It is always
better to analyze them by using simulations.
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PATTERN NOISE IN ?? MODULATOR
The question to be asked is why are this tones
dangerous in the signal bandwidth? The answer to
this question lies in the fact that all the
analysis made earlier on was based on the white
noise approximation and the problem with the
tones is that they are much above the expected
noise floor. Hence the true signal to noise ratio
is much lesser than what was expected from the
analysis.
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PATTERN NOISE IN ?? MODULATOR
Its generally said that the pattern noise is
visible only for slow moving inputs (not just
DC). To understand this more clearly assume the
input signal is a sinusoid with an input
frequency of fm. If fm is a factor of fs then
every time a new period of the sine wave starts
the SDM will generate the same output as it
generated in the earlier period. This means the
output will also be changing with a frequency of
fm. Hence the output will have tones at the
harmonics of the input sinusoidal signal. If fm
is very small then some of these harmonics will
lie in signal bandwidth and the SNR will be
lesser than expected.
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PATTERN NOISE IN ?? MODULATOR
Pattern Noise Reduces Effective Bits.
The frequency domain output of the SDM shows
tones and a noise floor. Consider them this noise
to be made of two components 1. Tones 2. Random
noise. Therefore in time domain these tones will
give rise to impulses (if a large number of tones
exist in the signal bandwidth). Since there is
random noise, the impulse train will have a
slightly varying magnitude but the frequency of
repetition will be equal to the fundamental
frequency. When these impulses are of the order
of 2 or 3 LSBs. This means ENOB is lesser then
was expected.
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SECOND ORDER ?? MODULATOR
The 2nd order modulator has one delaying and one
non-delaying integrator. Note that the last loop
with the quantizer must have one unit of delay
for stability. The z-domain transfer function of
the second order modulator is given by
Y(z) z-1X(z) (1-z-1)2 E(z) NTF (1-z-1)2
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SECOND ORDER ?? MODULATOR
We can calculate the in band noise power of a
second order ?? modulator to obtain
Giving us a noise figure of
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SECOND ORDER ?? MODULATOR
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INTEGRATOR OVERLOAD
In second order modulator with a single delaying
integrator, simulations show that the maximum
outputs of the two integrators increase as the
signal level increase. Very often, they are
several times the full scale analog input range.
The following table contains data from
simulations. The output levels indicated are the
maximum levels at the output of the two
integrators.
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INTEGRATOR OVERLOAD
It is seen that the levels increase as the input
value increases. This reduces the dynamic range
of the modulation since the integrations will now
saturate. The 2nd order modulator can be modified
as follows
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INTEGRATOR OVERLOAD
The linearized transfer function is Y(z) X (z)
. z-2 (1 z-1)2E(z) The signal levels at the
output of the integrators are now the following
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INTEGRATOR OVERLOAD
       The signal levels at the first integrator
output is reduced. However the second integrator
output levels are still high.          The SNR
in the two cases remains the same.          The
circuit specifications are now more relaxed since
there are two units of delay in the loop.
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INTEGRATOR OVERLOAD
We need to reduce the output levels in the second
integrator. For this we need to alter the gain
just before the second integrator. Let us see the
effect of altering this gain.
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INTEGRATOR OVERLOAD
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INTEGRATOR OVERLOAD
Therefore, even though the linearized transfer
function has changed, there is no change in the
actual output. This is because we have a two
level quantizer, the output of which depends only
on the polarity and not the magnitude of the
input. The quantizer effectively acts as an AGC
and makes the overall gain 1. ?The second
integrator gain can be adjust to reduce the
integrator output levels. Typically it is made
less than one. For a gain of ½, the integrator
output levels are the following
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INTEGRATOR OVERLOAD
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CIRCUIT NOISE
The sizes of the input capacitors should be
chosen both on the basis of slow rate as well as
thermal noise considerations. Thermal noise is
basically introduced by non-zero resistance of
the sampling switches. The baseband component of
this noise is approximately proportional to
(kT/C)(1/OSR) where C is the sampling
capacitor. If the OSR 256, C 1pF , the noise
power will be 1.625 x 10-11 Joules. The total
quantization noise power in baseband at this OSR,
with quantizer levels ? 1 is 5.9 x 10-12
Joules. Choose larger capacitance.
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SAMPLING JITTER
Sampling Clock Jitter results in non uniform
sampling, increasing total noise power in the
quantizer output. For a sinusoidal input with
amplitude A and frequency fx
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SAMPLING JITTER
If the jitter is assumed to be an uncorrelated
Gaussain random process (white), with standard
deviation ?t, the average power of this error
signal is
Since this is assumed to be white, the total
error power in baseband is
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IMPLEMENTATION IMPERFECTIONS
Supposing the two integrators have the following
transfer functions
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IMPLEMENTATION IMPERFECTIONS
Assume A1A2 (the two opamp have the gain).
Generally we can neglect the effect of the
denominator and obtain NTF (1 ?z-1)2
(1-?)4 is the unshaped noise, 2(1-?)2 ? ?2 is
the 1st order shaped noise and ?2 ?4 is the
2nd order shaped noise.  To make sure we get
second shaped, we need A ? OSR.
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IMPLEMENTATION IMPERFECTIONS
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?? AD Converter
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SIGNAL OUTPUTS OF ?? MODULATOR
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?? D/A CONVERTER
The sigma Delta D/A converter has a similar
topology to the A/D converter. Here the input
digital signal first goes through an
interpolation filter, where it is upsampled and
low pass filtered. After this it is fed to the
modulator. The output of the modulator is a
single bit signal, that comes at rate much higher
than the Nyquist rate. The output of the
modulator is ample and held and low pass filtered
to give the analog output.
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?? D/A CONVERTER
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?? D/A CONVERTER
The input to the modulator is a 12 bit signal
that is upsampled. The clock rate is much higher
than the Nyquist rate. The modulator is a second
order modulator and the topology is the same as
the A/D converter. All numbers are in the 2s
complement form. A one bit quantizer in this
case, would simple keep the MSB and throw out all
the other bits. The D/D converter converts the
one bit quantized output to 14 bit positive or
negative number as shown.
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AT LAST
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