Dominance Fault Collapsing

1
Dominance Fault Collapsing

• - Alok Doshi

ELEC 7250 Spring 2004
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Fault Collapsing

• The basic idea behind fault collapsing is to
  reduce the number of faults that have to be
  considered during the test generation process, in
  turn reducing the size of the test vector set.
• Fault collapsing eliminates those faults that can
  be detected by tests generated for some other
  faults.

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Dominance Fault Collapsing

• If all tests of fault F1 detect another fault
  F2, then F2 is said to dominate F1.

F1
All tests of F2
s-a-1
001 110 010 000 101
100
011
s-a-1
s-a-1
Only test of F1
s-a-1
s-a-0
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Structural Dominance Fault Collapsing

• Summarized as follows
• An ninput Boolean gate requires n1 single stuck
  at faults to be modelled.
• To collapse faults of a gate, all faults from
  output can be eliminated retaining one type
  (s-a-1 for AND and NAND s-a-0 for OR and NOR) of
  fault on each input and the other type (s-a-0 for
  AND and NAND s-a-1 for OR and NOR) on any one of
  the inputs.
• The output faults of the NOT gate, the non
  inverting buffer, and the wire can be removed as
  long as both faults on the input are retained. No
  collapsing is possible for fanout. Also no
  collapsing is possible for the XOR and XNOR gates.

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Algorithm

1. Read the bench file and convert it to a format
   easy to access.
2. Now read this file and take all data into the
   structure. Check for errors made in the bench
   file.
3. Find all fanouts of a gate.
4. Find all primary inputs with fanouts.
5. Find primary inputs without fanouts and whose
   output feeds into a gate which has all its inputs
   as primary inputs without fanouts.
6. Find all gates into which the primary inputs with
   fanouts feed.
7. Find all gates which are fanouts of other gates.
   (These should not include the gates that have any
   of its input as a primary input).
8. Calculate collapse ratio.

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Example
6
1
10
2
12
7
14
11
3
13
8
15
4
9
5
7
Example
6
1
10
2
12
7
14
11
3
13
8
15
4
9
5
8
Example
6
1
10
2
12
7
14
11
3
13
8
15
4
9
5
9
Example
6
1
10
2
12
7
14
11
3
13
8
15
4
9
5
10
Example
6
1
10
2
12
7
14
11
3
13
8
15
4
9
5
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Results
C17 ALU(XOR) ALU(NAND) Full Adder 8-bit Adder
Total Faults 54 532 676 80 634
Equivalence collapsed faults 22 237 301 38 290
Dominance collapsed faults 16 208 248 30 226
Fault Coverage (Equivalence) 1 - 0.9734 1 1
Fault Coverage (Dominance) 1 - 0.9677 1 1
Collapse Ratio (Equivalence) 0.407 0.4452 0.475 0.457
Collapse Ratio (Dominance) 0.296 0.366 0.390 0.375 0.356
of Vectors (Equivalence) 10 - 36 8 20
of Vectors (Dominance) 10 - 48 8 16
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Redundant faults in ALU(NAND)

• Equivalence Dominance
• 86 2 1 ---------- 74 1 0
• 58 1 1 58 1 1
• 88 2 1 ---------- 77 1 0
• 63 1 1 63 1 1
• 90 2 1 ---------- 80 1 0
• 67 1 1 67 1 1
• 92 2 1 ---------- 83 1 0
• 70 1 1 70 1 1