Fast, Asynchronous SRAM

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Fast, Asynchronous SRAM

• Discussion D8.2

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buff3.vhd
en
library IEEE use IEEE.STD_LOGIC_1164.all entity
buff3 is generic (widthpositive) port(
input in STD_LOGIC_vector(width-1 downto 0)
en in STD_LOGIC output out
STD_LOGIC_vector(width-1 downto 0) ) end
buff3 architecture buff3 of buff3 is begin
output lt input when en '1' else (others gt
'Z') end buff3
input
output
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RAM Module
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RAM1
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library IEEE use IEEE.std_logic_1164.all use
IEEE.std_logic_arith.all entity clock_pulse2
is port ( inp, cclk, clr in
std_logic outp1 out std_logic outp2 out
std_logic ) end clock_pulse2
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architecture clock_pulse2_arch of clock_pulse2
is signal delay1, delay2, delay3, delay4
std_logic begin process(cclk, clr)
begin if clr '1' then
delay1 lt '0' delay2 lt '0'
delay3 lt '0' delay4 lt '0' elsif
cclk'event and cclk'1' then delay1 lt
inp delay2 lt delay1 delay3 lt
delay2 delay4 lt delay3 end if end
process outp1 lt delay1 and delay2 and (not
delay3) outp2 lt delay1 and delay2 and
delay3 and (not delay4) end clock_pulse2_arch
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Counter clock Address
WE
BTN2
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library IEEE use IEEE.STD_LOGIC_1164.all use
IEEE.STD_LOGIC_unsigned.all entity ram1 is
port( mclk in STD_LOGIC BTN3 in
STD_LOGIC BTN2 in STD_LOGIC BTN0 in
STD_LOGIC SW in STD_LOGIC_VECTOR(7 downto
0) AN out STD_LOGIC_VECTOR(3 downto 0)
AtoG out STD_LOGIC_VECTOR(6 downto 0) LD
out STD_LOGIC_VECTOR(7 downto 0) A out
STD_LOGIC_VECTOR(17 downto 0) dp out
STD_LOGIC LB1 out STD_LOGIC UB1 out
STD_LOGIC CE1 out STD_LOGIC OE out
STD_LOGIC WE out STD_LOGIC IO10 inout
STD_LOGIC_VECTOR(15 downto 0) ) end ram1
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begin dp lt '1' clr lt BTN3 OE lt
oen IO10(7 downto 0) lt IOdata IO10(15
downto 8) lt "ZZZZZZZZ" A lt qout LD lt
qout(7 downto 0) WE lt outp1 nand BTN2 oen
lt BTN2 UB1 lt '1' LB1 lt '0' CE1 lt
'0' ground lt "00000000" load lt not BTN2
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U0 clock_pulse2 port map (inp gt BTN0, cclk
gt cclk, clr gt clr, outp1 gt outp1, outp2 gt
outp2) U1 count18 port map (clk gt
outp2, clr gt clr, q gt qout) U2 x7segb
port map (x(15 downto 8) gt ground, x(7 downto
0) gt xin, clr gt clr, cclk gt cclk, AN gt AN,
AtoG gt AtoG) U3 buff3 generic map(width
gt bus_width) port map (input gtSW, en gt oen,
output gt IOdata) INreg reg generic
map(width gt bus_width) port map (d gt IOdata,
load gt load, clr gt clr, clk gtoutp2, q gt
xin) end ram1
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