ALU%20and%20Shifters%20Lab%202

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ALU and ShiftersLab 2

• Mano and Kime
• Sections 7-6 7-8

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ALU and Shifters

• ALUs
• Shifters
• Lab 2

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n-Bit ALU
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Arithmetic Circuit
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ALU and Shifters

• ALUs
• Shifters
• Lab 2

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4-Bit Basic Shifter
S 00 No shift S 01 Right shift S 10
Left shift
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4-Bit Barrel Shifter
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ALU and Shifters

• ALUs
• Shifters
• Lab 2

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Lab 2 ALU1Shifting, Increment and Decrement
Instructions
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alu1 entity
library IEEE use IEEE.std_logic_1164.all use
IEEE.std_logic_unsigned.all   entity alu1 is
generic(widthpositive) port ( a in
STD_LOGIC_VECTOR(width-1 downto 0) sel
in STD_LOGIC_VECTOR(2 downto 0) y out
STD_LOGIC_VECTOR(width-1 downto 0) ) end
alu1
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architecture alu1_arch of alu1 is begin alu_1
process(a, sel) variable true, false
STD_LOGIC_VECTOR (width-1 downto 0) begin --
true is all ones false is all zeros for i
in 0 to width-1 loop true(i) '1'
false(i) '0' end loop case sel is
when "000" gt -- 1 y lt a 1
when "001" gt -- 1- y lt a -
1 when "010" gt --
invert y lt not a when "011"
gt -- 2 y lt a(width-2 downto 0) '0'
when "100" gt -- U2/ y lt '0'
a(width-1 downto 1)
when "101" gt -- 2/ y lt a(width-1)
a(width-1 downto 1) when "110"
gt -- TRUE y lt true
when others gt -- FALSE y
lt false end case end process
alu_1 end alu1_arch
Note forloop