Chapter 7 Input/Output

1
Chapter 7Input/Output
Continued
2
Interrupt Physical Model

• CPU
• Memory
• Device

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Interrupt Physical Model

• CPU
• General Purpose Registers
• PC Storage R7
• Stack Pointer R6
• Program Status Word (PSW) Includes
• State
• Program Priority
• Condition Codes (CC)
• User stack Pointer Storage USP.saved
• Supervisor Stack Pointer Storage SSP.saved
• Hardware to communicate over the BUS
• Memory
• User program
• Interrupt Service Routine
• Operating System
• Interrupt Vector Table
• Includes an entry that points to the Interrupt
  Service Routine (Interrupt vector )
• Device
• Status/Control Register(s) Includes

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Interrupt Sequence

1. What does the programmer do?
2. What does the computer do?

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Interrupt Sequence

• Programmer Action
• Enable Interrupts by setting intr
  enable bit in Device Status Reg
• Enabling Mechanism for device
• When device wants service, and
• its enable bit is set (The I/O device
  has the right to request service), and
• its priority is higher than the
  priority of the presently running program, and
  
• execution of an instruction is
  complete, then
• The processor initiates the interrupt
• Process to service the interrupt
• The Processor saves the state of the
  program (has to be able to return)
• The Processor goes into Privileged Mode (PSR
  bit 15 cleared)
• Priority level is set (established by the
  interrupting device)
• The (USP), (R6) ? USP.saved register
  (UserStackPointer.saved)
• The (SSP.saved) ? R6 (SupervisorStackPointer)
• The (PC) and the (PSR) are PUSHED onto the
  Supervisor Stack
• The contents of the other registers are not
  saved. Why?
• The CCs are cleared

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DMA Function

• DMA controller(s) takes over from CPU for I/O
• Additional Module(s) attached to bus to control
  DMA operation

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Typical DMA Module Diagram
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DMA Operation

• CPU tells DMA controller-
• Read/Write
• Device address
• Starting address of memory block for data
• Amount of data to be transferred
• CPU carries on with other work
• DMA controller deals with transfer
• DMA controller sends interrupt when finished

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DMA TransferCycle Stealing

• DMA controller takes over bus for a cycle
• Transfer of one word of data
• Not an interrupt
• CPU does not switch context
• CPU suspended between bus cycles
• i.e. before an operand or data fetch or a data
  write
• Slows down CPU but not as much as CPU doing
  transfer

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DMA and Interrupt Breakpoints During an
Instruction Cycle
What could be wrong with this?
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Aside

• What effect does caching memory have on DMA?
• What effect does use of DRAMs have on DMA ?

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DMA Configurations (1)

• Single Bus, Detached DMA controller
• Each transfer uses bus twice
• I/O to DMA then DMA to memory
• CPU is suspended twice

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DMA Configurations (2)

• Single Bus, Integrated DMA controller
• Controller may support gt1 device
• Each transfer uses bus once
• DMA to memory
• CPU is suspended once

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DMA Configurations (3)

• Separate I/O Bus
• Bus supports all DMA enabled devices
• Each transfer uses bus once
• DMA to memory
• CPU is suspended once

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I/O Channels

• I/O channels are processors dedicated to I/O
• e.g. 3D graphics cards
• CPU instructs I/O controller to do transfer
• I/O controller does entire transfer from one or
  many devices
• Makes transfers less visible to CPU
• Improves speed
• Takes load off CPU

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I/O Channel Architecture
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Interfacing Options

• Parallel
• - PCI
• - SCSI
• Serial
• - RS 232
• Local Networks
• - Ethernet
• Newer technologies
• - FireWire
• - InfiniBand
• - USB
• Wireless
• - BlueTooth
• - WiFi
• Automation
• - CAN

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Intel 82C55A Programmable Peripheral Interface
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Keyboard/Display Interfaces to 82C55A
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Layering Example OSI Network Layers
International Standards Organizations (ISO) Open
Systems Interconnection (ISO) Model

• The Physical Layer describes the physical
  properties of the various communications media,
  as well as the electrical properties and
  interpretation of the exchanged signals.
• Example this layer defines the size of
  Ethernet coaxial cable, the type of BNC connector
  used, and the termination method.
• The Data Link Layer describes the logical
  organization of data bits transmitted on a
  particular medium.
• Example this layer defines the framing,
  addressing and check-summing of Ethernet packets.
  
• The Network Layer describes how a series of
  exchanges over various data links can deliver
  data between any two nodes in a network.
• Example this layer defines the addressing
  and routing structure of the Internet.
• The Transport Layer describes the quality and
  nature of the data delivery.
• Example this layer defines if and how
  retransmissions will be used to ensure data
  delivery.
• The Session Layer describes the organization of
  data sequences larger than the packets handled by
  lower layers.
• Example this layer describes how request and
  reply packets are paired in a remote procedure
  call.
• The Presentation Layer describes the syntax of
  data being transferred.
• Example this layer describes how floating
  point numbers can be exchanged between hosts with
  different math formats.
• The Application Layer describes how real work
  actually gets done.
• Example this layer would implement file
  system operations.

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Simple Example OF 7 Layer OSI Model

• Application Layer Set of C Instructions, Set of
  Data
• I0 I1 I2 . IN Do D1 D2 Dm
• Presentation Layer ASCII Coding
• ASC I0 I1 I2 . IN Do D1 D2 Dm
• Session Layer What process at computer x is
  communicating with what process at computer y
• X4 Y6 ASC I0 I1 I2 . IN Do D1 D2
  Dm
• Transport Layer Guaranteed Transmission,
  sequentially numbered packets of 4096 bytes
• GT4 P34 X4 Y6 ASC I0 I1 I2 . IN Do D1
  D2 Dm PCKSUM
• Network Layer Path through Network
• N23 N3 N53 GT4 P34 X4 Y6 ASC I0 I1 I2
  . IN Do D1 D2 Dm PCKSUM
• Data Link Layer Serial 256 bytes per frame
• STRT TN23 N3 N53 GT4 P34 X4 Y6 ASC I0
  I1 I2 . IN Do D1 D2 Dm PCKSUMCHKSM
• Physical Layer 9600Baud, Coax cable - Start
  .Parity Stop Stop

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Serial - RS 232

• UART (Universal Asynchronous Receiver
  Transmitter)
• Serial interface on a chip
• Historically very significant
• After 30 years, still a standard

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RS232 Character transmission
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UART Block Diagram
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Connector Wiring Null Modem
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UART Application
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Ethernet

• CSMA/CD (Carrier Sense Multiple Access/Collision
  Detection)
• A local area network access method in which
  contention between two or more stations is
  resolved by collision detection.
• When two stations transmit at the same time, they
  both stop and signal a collision has occurred.
  Each then tries again after waiting a
  predetermined time period. To avoid another
  collision, the stations involved each choose a
  random time interval to schedule the
  retransmission of the collided frame.
• To make sure that the collision is recognized,
  Ethernet requires that a station must continue
  transmitting until the 50 microsecond period has
  ended. If the station has less than 64 bytes of
  data to send, then it must pad the data by adding
  zeros at the end.

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Bob Metcalfs Ethernet Concept - 1976
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Network Reference model - Ethernet
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Ethernet packet
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Ethernet block diagram
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IEEE 1394 FireWire (Competitor to USB)

• High performance serial bus
• Fast
• Low cost
• Easy to implement
• Also being used in digital cameras, VCRs and TV

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FireWire Configuration

• Daisy chain
• Up to 63 devices on single port
• Really 64 of which one is the interface itself
• Up to 1022 buses can be connected with bridges
• Automatic configuration
• No bus terminators
• May be tree structure

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Simple FireWire Configuration
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FireWire 3 Layer Stack

• Physical
• Transmission medium, electrical and signaling
  characteristics
• Link
• Transmission of data in packets
• Transaction
• Request-response protocol

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FireWire Protocol Stack
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FireWire - Physical Layer

• Data rates from 25 to 400Mbps
• Two forms of arbitration
• Based on tree structure
• Root acts as arbiter
• First come first served
• Natural priority controls simultaneous requests
• i.e. who is nearest to root
• Fair arbitration
• Urgent arbitration

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FireWire - Link Layer

• Two transmission types
• Asynchronous
• Variable amount of data and several bytes of
  transaction data transferred as a packet
• To explicit address
• Acknowledgement returned
• Isochronous
• Variable amount of data in sequence of fixed size
  packets at regular intervals
• Simplified addressing
• No acknowledgement

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FireWire Subactions
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InfiniBand

• I/O specification aimed at high end servers
• Merger of Future I/O (Cisco, HP, Compaq, IBM) and
  Next Generation I/O (Intel)
• Version 1 released early 2001
• Architecture and spec. for data flow between
  processor and intelligent I/O devices
• Intended to replace PCI in servers
• Increased capacity, expandability, flexibility

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InfiniBand Architecture

• Remote storage, networking and connection between
  servers
• Attach servers, remote storage, network devices
  to central fabric of switches and links
• Greater server density
• Scalable data centre
• Independent nodes added as required
• I/O distance from server up to
• 17m using copper
• 300m multimode fibre optic
• 10km single mode fibre
• Up to 30Gbps

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InfiniBand Switch Fabric
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InfiniBand Operation

• 16 logical channels (virtual lanes) per physical
  link
• One lane for management, rest for data
• Data in stream of packets
• Virtual lane dedicated temporarily to end to end
  transfer
• Switch maps traffic from incoming to outgoing lane

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InfiniBand Protocol Stack