3'3'3 Available Devices BiCMOS

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• 3.3.3 Available Devices -- BiCMOS
• All devices from CMOS LDD NMOS, SDD PMOS, ED HV
  NMOS, Resistors (Poly-1, PSD, NSD, and Nwell)
  
• - others

Ex) Extended Drain High-Voltage NMOS
LAYOUT
XSECTION
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• 3.3.3 Available Devices -- BiCMOS
• All devices from CMOS LDD NMOS, SDD PMOS, ED HV
  NMOS, Resistors (Poly-1, PSD, NSD, and Nwell)
  
• - others

Ex) Extended Drain High-Voltage NMOS
LAYOUT
XSECTION
3

• (1) NPN Transistor
• Collector NWell NBL Deep-N NSD (for
  contact)
• Base PBase (3rd counter doping) PSD (for
  contact)
• Emitter NSD (emitter diffusion and contact)
• Comments
• Emitter area EBJ area for injection
• PBase 3rd impurity doping ? higher Irec (IB
  Irec ..) ? lower b. ? b is
  typically aimed at 50 or 75(1 - 0.5)
• Without Deep-N, Collector has too high
  Resistance ? soft transistion between
  Saturation and Active regions ?
• Zeners do not require deep-N because not much
  current flows in Collector.
• BiCMOS NPN vs. Standard NPN

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NPN Bipolar
Layout
Xsect
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NPN Bipolar
Layout
Xsect
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• (2) Substrate PNP
• Same as in Polygate CMOS
• PSD implant into NWELL ? Emitter
• NWELL ? Base
• P-epi on P-sub ? Collector

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Substr. PNP (same as in CMOS)
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Substr. PNP (same as in CMOS)
Lateral PNP (BiCMOS only)
-- surrounds both C E LOCOS blocks B region
-- the Pbase diff of NPN helps Sidewall
Injection/Collection for higher Beta
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Substr. PNP (same as in CMOS)
Lateral PNP (BiCMOS only)
-- surrounds both C E LOCOS blocks B region
-- the Pbase diff of NPN helps Sidewall
Injection/Collection for higher Beta
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• (3) Lateral PNP
• P-Base diffusion of NPN ? Emitter Collector of
  PNP,
  formed in NWELL.
• Role of NBL in lateral PNP
• Depletion stop
• Blocks punchthrough breakdown
• Allows deeper Pbase (NPN) implant for E C (rid
  of shallower PSD implant) ? Increase
  Sidewall area ! ? higher b 100 (vs. b
  lt10 w/o NBL)

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Lateral vs. Substrate PNP
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• (4)Resistor
• PBase resistor in NWELL
• Rs 500 W/sq. for lightly doped Base
• If too lightly doped ? surface depletion is
  problem.
• Not much better than Poly resistors, only if
  larger area is affordable.

Layout
Xsection
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• SCMOS Layout Questions about
• Verical NPN Bipolar Transistor gt Y
• Lateral PNP Transistor gt No
• Poly Capacitor gt Y

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AMI_ABN Run Examples
NPN b 110 - 130 VA about 50 V
Poly Capacitor C 0.6 fF/mm2