Asynchronous 8051 Microcontroller Presentation

1
Asynchronous 8051 Microcontroller Presentation
By Ryan Mabry April 18, 2005
2
Agenda

• 8051 Background
• Motivation
• Architecture
• Design Flow
• Design Implementation
• Results
• Challenges
• Conclusion

3
8051 Background

• Developed by Intel in 1980
• Widely used in embedded systems
• Very popular after 25 years on the market
• Official 8051 family designation is MCS 51
• Based on Harvard Architecture
• Separate memory for instructions and data
• ROM stores program instructions
• RAM stores program data

4
8051 Background Continued

• 8051 Predecessor was the 8048
• Used in IBMs first PC keyboard
• Enhanced version of 8051 is 8052
• Increased Internal Memory Capacity
• Additional Timer
• More Registers

5
Motivation

• Project is based off VHDL synthesizable 8051
  model
• developed by University of Californias Dalton
  Project
• (http//www.cs.ucr.edu/dalton/8051)
• Two Goals
• A) Develop asynchronous 8051
• B) Use synchronous design tools in the process
• Asynchronous Advantages
• A) Lower Power Consumption
• B) No clock skew

6
Motivation Continued

• Asynchronous Disadvantages
• A) No complete design solution tools
• B) No global clock communication must be done
• through handshaking or other methods
• C) Must ensure timing and data integrity when
  using
• asynchronous communication methods

7
Synchronous Architecture

8
Asynchronous Architecture

9
Architecture Differences

• Clock is generated onboard asynchronous 8051
• Clock is stopped while controller waits for ALU
  to complete
• an operation
• - Implemented through handshaking signals
• generated by ALU and Controller Wrappers
• No excess cycles in asynchronous controller
• - Defined in synchronous version as clock cycles
  
• where controller is doing nothing and waiting
  for
• ALU to complete an operation

10
Asynchronous Design Flow


11
Asynchronous Design Flow Continued

• Functional Simulation Verify Functionality Of
  Design
• A) Standard VHDL Compilers cannot synthesize
• VHDL code that implements asynchronous logic
• B) This project used Modelsim
• C) Compare controller registers, memory contents
• and instructions executed in asynchronous and
• synchronous versions verify to be the same
• Synchronous Block Synthesis Synthesize
  synchronous
• parts of both 8051 microcontrollers. This
  project used
• Ambit Buildgates.
• Behavioral Code -gt Verilog Netlist

12
Asynchronous Design Flow Continued

• Timing Analysis Generate Delay Numbers
• A) Cadence Encounter generates parasitics for
  circuits
• B) Use Synopsys Primetime for critical path
  analysis
• C) Import parasitics and verilog netlist into
  Primetime
• D) Remove successive ALU Operations to get delay
  
• numbers
• IE Remove division case from ALU to obtain
• critical path delay for multiplication
• E) Also generate critical path numbers for RAM,
  ROM,
• decoder, and controller modules

13
Asynchronous Design Flow Continued

• Asynchronous Wrapper Design
• A) Implement delay elements for wrappers in
• Cadence Composer schematic editor
• B) Combinational logic elements in wrappers
• can be designed in VHDL code and then imported
• C) Wire two parts together in schematic
• Timing Simulation
• Unable to test implementation of asynchronous
  design
• since university does not have post-synthesis
  timing
• simulator installed.

14
Design Implementation - Handshaking

• Controller needs ALU Operation to be performed
• A) Assert request line
• B) Stop Clock
• Once ALU Operation is finished
• A) Assert acknowledge line
• B) Start Clock

• Deassert request Line
• Deassert acknowledge line

15
Design Implementation ALU Wrapper
16
Design Implementation ALU Wrapper Continued

• Remove operations from ALU to obtain delay
  numbers
• Buffers used as building block for each delay
  element
• - Delay of 114ps (Used 100ps to simplify design)
• Primetime was used for critical path analysis
• Apply 50 safety margin to initial numbers to
  account for
• operating conditions temperature changes and
• voltage fluctuations

17
Design Implementation Controller Wrapper

• Asserts request signal while controller is
  waiting for ALU
• to complete operation
• Deasserts request signal once acknowledge signal
  from
• ALU wrapper is received
• Implemented in VHDL code

18
Design Implementation Controller Modifications

• Excess Cycles Eliminated
• Example ADDC_1 instruction takes 8 clock cycles
• in synchronous controller and 6 clock cycles in
• asynchronous controller

Cycles ES_5 and ES_6 are excess cycles Eliminated
in asynchronous version
19
Design Implementation Clocking Unit

• When req1 and ack0 clock is stopped.
  Otherwise
• behaves as a synchronous clock
• Length of inverter chain is longer than critical
  path in
• RAM to avoid timing violations
• Critical path in RAM module is 30.9ns
• Since inverter has delay of 50ps, inverter chain
  must be
• 682 inverters long

20
Results

• Targeted VTVT standard cell library developed by
  Virginia
• Tech VLSI for Telecommunications.
• Asynchronous 8051 consumes more area due to
  onboard clock and wrappers. RAM dominates both
  chip areas
• Asynchronous Cell Area 72400
• Synchronous Cell Area 65662
• Divmul program on Dalton website used to roughly
  benchmark designs in Modelsim
• Asynchronous Simulation Time 172,030ns
• Synchronous Simulation Time 221,390ns
• Asynchronous 8051 is roughly 28.7 faster while
  using 10 more area than synchronous version

21
Challenges

• Had to learn all of the different tools
• A) Technical assistance was available for Ambit
  Buildgates and Cadence Encounter
• B) Resorted to user manuals and the Internet for
  Synopsys Primetime
• Learned other tools not necessary to design flow
• - Time spent learning Synopsys Design Analyzer
  and Timemill could have been better spent in
  later stages of design flow

22
Conclusion

• A lot of work to change existing synchronous
  design to asynchronous design
• Use of synchronous design tools in asynchronous
  design flow made process much easier
• Since no post-synthesis timing simulators are
  installed, it is impossible to verify the
  correctness of the asynchronous design
• I would like to thank Narender Hanchate for his
  time in helping me learn most of the tools used
  in this project