Power Optimization Toolbox

1
Magic An Industrial-Strength Logic
Optimization, Technology Mapping, and Formal
Verification System
Alan Mishchenko UC Berkeley
2
Overview

• Motivation
• Big picture
• Problem representation
• Algorithms
• Sequential synthesis
• Combinational synthesis with choices
• Technology mapping
• Minimum-perturbation retiming
• Experimental results
• Future work

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Historical Perspective
Design size, gate count
ABC, Magic
1,000,000
SIS, VIS, MVSIS
10,000
Espresso, MIS, SIS
100
And-Inverter Graphs
Binary Decision Diagrams
Sum-of-products
Conjunctive normal forms
10
Truth tables
Time, years
1950-1970
1980
1990
2000
2010
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Motivation

• ABC is a public-domain system for logic synthesis
  and formal verification under development at
  Berkeley since 2005
• A successor of Espresso, MIS, SIS, VIS, MVSIS
• The baseline version of ABC is not applicable to
  industrial designs because it does not support
• Complex flops
• Multiple clock domains
• Special objects (adders, RAMs, DSPs, etc)
• Standard-cell libraries
• A fresh start, called Magic, was taken in Fall
  2009
• Includes new design database that supports these
• Integrates application packages for better
  memory/runtime
• Achieves better scalability

5
Big Picture
Verilog, EDIF, BLIF
Programmable APIs
A. Mishchenko, N. Een, R. K. Brayton, S. Jang, M.
Ciesielski, and T. Daniel, "Magic An
industrial-strength logic optimization,
technology mapping, and formal verification
tool". Proc. IWLS'10.
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Application Packages

• Combinational optimization
• AIG rewriting
• Choice computation
• Technology mapping
• Sequential optimization
• Retiming
• Merging equivalence nodes
• Technology mapping
• Mapping with choices
• Speedup
• Verification
• Simulation
• Comb equivalence checking
• Seq equivalence checking

• Framework
• Design database
• File input / output
• Programmable APIs

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Representations

• Netlist
• Original / current / resulting design with
  industrial stuff
• AIG The main data-structure of ABC / Magic
• Represents local / global functions
• Gets synthesized / mapped / verified
• Logic network
• Represents the result of technology mapping

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AIG Definition and Examples
AIG is a Boolean network composed of two-input
ANDs and inverters
cdab 00 01 11 10
00 0 0 1 0
01 0 0 1 1
11 0 1 1 0
10 0 0 1 0
F(a,b,c,d) ab d(acbc)
6 nodes 4 levels
F(a,b,c,d) ac(bd) c(ad) ac(bd)
bc(ad)
cdab 00 01 11 10
00 0 0 1 0
01 0 0 1 1
11 0 1 1 0
10 0 0 1 0
7 nodes 3 levels
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AIG A Unifying Representation

• An underlying data structure for various
  computations
• Representing both local and global functions
• Used in rewriting, resubstitution, simulation,
  SAT sweeping, induction, etc
• A unifying representation for the whole flow
• Synthesis, mapping, verification pass around AIGs
• Stored multiple structures for mapping (AIG with
  choices)
• The main functional representation in ABC
• Foundation of contemporary logic synthesis
• Source of signature features (speed,
  scalability, etc)

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Magic Optimization Flow

• The design is entered from file or through
  programmable APIs
• Internal representation is based on a
  light-weight data-structure for improved memory
  and runtime
• Sequential synthesis is applied to detect and
  merge seq equiv objects
• Combinational synthesis and mapping are iterated
  several times, while saving the best result
• Optionally, min-perturbation retiming and
  resynthesis are applied to reduce delay/area
  after mapping
• The design is saved into file or through
  programmable APIs
• Verification is performed between any two points
  in the flow

Inputting the design
Sequential synthesis
Comb synthesis with choices
Verification
Tech mapping
Retiming and resynthesis
Outputting the design
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Sequential Synthesis (Motivation)
F
G

• Combinational equivalence
• Two functions, F and G, produce the same output
  for all input combinations
• Sequential equivalence
• Two functions, F and G, produce the same value
  for all reachable states

00 01 11 10
00 0 1 0 0
01 0 1 1 0
11 1 1 0 0
10 0 1 0 0
00 01 11 10
00 0 1 0 0
01 0 1 1 0
11 1 1 0 0
10 0 1 0 0
Complete Boolean space
is shown by highlighting
G
F
00 01 11 10
00 0 1 0 0
01 0 1 0 0
11 0 1 0 0
10 0 1 0 0
00 01 11 10
00 0 1 1 0
01 0 0 0 0
11 0 0 0 0
10 0 0 0 0
Reachable state space of 1-hot encoding is shown
by highlighting
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Sequential Synthesis

• Detect, prove, and merge sequentially equivalent
  nodes
• Seq equiv nodes are equivalent on reachable
  states
• Special case Comb equiv nodes are equivalent on
  for any state
• Observations
• Can be done using simulation and SAT (without
  BDDs)
• Leads to substantial reduction for large designs
  (gt 10 in area)
• Works for large designs (10-15 minutes for 1M
  gates)

B
A
B
A
A. Mishchenko, M. L. Case, R. K. Brayton, and S.
Jang, "Scalable and scalably-verifiable
sequential synthesis", Proc. ICCAD'08.
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Experiment Results
Results collected using a suite of 20 industrial
designs
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Comb Synthesis (AIG rewriting)

• Restructures AIG by applying the following
  transforms
• Rewriting/refactoring/redecomposition
• Tree-balancing
• Resubstitution
• Minimization with don't-cares, etc
• Case study AIG rewriting

Pre-compute AIG subgraphs for F abc
Rewriting node A
?
a
b
a
a
c
b
c
b
a
c
Subgraph 1
Subgraph 2
Subgraph 3
A. Mishchenko, S. Chatterjee, and R. Brayton,
"DAG-aware AIG rewriting A fresh look at
combinational logic synthesis", Proc. DAC '06.
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Combinational Synthesis with Structural Choices

• Perform synthesis and keep track of changes
• Iterate fast local AIG rewriting with a global
  view (via hash table)
• Collect AIG snapshots and prove equivalences
  across them
• Use equivalences (choices) during technology
  mapping
• Observations
• Leads to improved QoR after technology mapping
• Successfully applied to 1M gate designs

Traditional synthesis
D1
D2
D3
D4
Synthesis with choices
D1
D4
HAIG
D2
D3
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Technology Mapping
Mapped network
AIG

• Customizable structural mapping with priority
  cuts
• Computes a small subset of cuts without impacting
  the QoR
• Uses structural choices
• Observations
• Controls QoR tradeoffs
• Minimizes delay/area, wire count, switching
  activity, etc
• Successfully applied to 1M gate designs

f
b
c
d
e
a
A. Mishchenko, S. Cho, S. Chatterjee, R. Brayton,
"Combinational and sequential mapping with
priority cuts", Proc. ICCAD '07.
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Minimum-Perturbation Retiming

• Reduces delay, while minimizing the number of
  flops moved
• Produces a trade-off delay gain vs. the number
  of flops moved
• Handles industrial stuff retimes over white
  boxes such as adders!
• Computes new initial state after backward
  retiming
• Allows the user to control the resources
• Desired delay gain
• Maximum allowed number of flops moved
• Maximum area increase after retiming
• Observations
• Can be useful before and after placement
• Can be implemented efficiently
• Runs in less than a minute for 1M gates

S. Ray, A. Mishchenko, R. K. Brayton, S. Jang,
and T. Daniel, "Minimum-perturbation retiming for
delay optimization". Proc. IWLS'10.
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Sequential Verification

• Property checking
• Takes design and property and makes a miter (AIG)
• Equivalence checking
• Takes two designs and makes a miter (AIG)
• The goal is to transform AIG until the output can
  be proved const 0
• Equivalence checking in Magic is based on the
  model checker that won Hardware Model Checking
  Competition in 2008 and 2010
• http//fmv.jku.at/hwmcc10/results.html

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A Naïve Way to Use ABC

• Convert all persistent logic to black boxes
• Box IOs are treated as PI/POs in synthesis
• Adverse effects
• Losing the correlation of box outputs/inputs
• Restricting synthesis due to broken logic paths
• Not being able to propagate delays through the
  boxes
• Sequential synthesis doesnt work well

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A Better Way to Use ABC

• Clock domains
• Represent clock signal in the data-base
• Annotate flops with their clock-domain number in
  the AIG
• Separate clock domains in sequential transforms
• Complex controls of the flops
• Use parametrized flop model
• Perform elaboration of control signals if needed
• Handle asynchronous reset carefully!
• Industrial primitives (adders, RAMs, DSPs, etc)
• Use boxes (black/white, comb/seq, merge/no_merge,
  etc)
• Currently propagates timing information, improves
  quality of synthesis
• Elaborate boxes for seq synthesis, but do not map
  them
• Need better support for user-specified attributes
  (dont-touch, etc)

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Experimental Setup

• Integrated Magic into an industrial FPGA
  synthesis flow
• Experimented with the full flow, including PR
• Did not use retiming
• Did not use post-placement re-synthesis
• Verified by running Magic and in-house simulation
  tools
• Experimented with 20 designs, from 175K to 648K
  LUT4
• Two experimental runs
• Reference stands for the typical industrial
  flow without Magic
• Magic stands for the new flow with Magic

Frontend
Magic
Backend
Design entry, high-level synthesis, quick mapping
Placement, routing, design rule checking, etc
Seq and comb synthesis, mapping, legalization
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Experimental Results
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Cumulative Improvement(retiming excluded)
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Future Work

• Continue to improve application packages
• AIG rewriting, tech-mapping, sequential
  synthesis, etc
• Improve integration of logic and physical
  synthesis
• Synthesis/mapping/retiming before placement
• Retiming/restructuring after placement
• Extend the flow to work for other technologies
• Macro cells
• Standard cells