Future Research in Computer Arithmetic

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Future Research in Computer Arithmetic

• September 28, 2007
• Eric Schwarz, IBM

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Topics

• Binary Multiplication
• Proofs of Overlapped Scanning Foundations
• 73 Counter Design Future
• Division
• Direct Division
• Remainder Avoidance active
• Decimal Floating-Point extremely active
• Pipelining Add
• Multiply
• Multiply-Add

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• Binary Multiplication

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Basics

• Recode multiplier and separate into digits
• Create multiples of the multiplicand
• Multiplex the multiples
• Sum all partial products in counter tree
• reduce final 2 partial products in CLA

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History of Overlapped Scanning

• A.D. Booth in 1951 showed overlapped scanning
• L. Rubinfield in 1975 proved radix-4 Booth
• S. Vassiliadis in 1989 proved Booth for any radix

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Fixed Point Multiplication in 1973
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Fixed Point Multiplication in 1991
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High Level Counters 73
US Patent 5,187,679 in 1993
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• Power6 and Z6 Decimal Floating Point Hardware

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Power6 and Z6 processors have DFU
Core
L2 Data
L2 Data
L3 Ctrl
L2 Ctrl
Mem Ctrl
Mem Ctrl
L2 Ctrl
L3 Ctrl
L2 Data
L2 Data
Core
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754R Decimal Floating Point Format

• IEEE 754R defines 2 formats
• Integer coefficient DPD (Densely Packed
  Decimal)
• Formats for 32,64,128 bit.
• C encodes 2 exponent bits and 1 decimal digit in
  5 bits.

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Power6 Decimal Floating Point Unit

• Cycle Time approx 5Ghz, 13 FO4 design
• Hardware executes 64-bit and 128-bit formats.
• 144-bit Dataflow can be split into two 72-bit
  pipes.
• DPD coefficients are decoded into BCD for
  execution.
• All cases are handled in hardware. (No Special
  Case Software Traps)

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Coefficient Dataflow
Multiple Generator
1X,3X,4X Registers
36 Digit Dataflow splits to Two 18 Digit Dataflows
Doubler Quintupler
A mux
B mux
Q
Expand DPD to BCD
Prescale Table
Expand DPD to BCD
Operand A Hi Register
Operand A Lo Register
Operand B Hi Register
Operand B Lo Register
Magnitude Calculations A-B B-A
Multiplication Partial Product Partial
Product Accumulate Generate
Q Correction and Multiplexers
Working Register Hi
Working Register Lo
Q
DEC to BIN BIN to DEC Converters
Compress BCD to DPD
Result Register Hi
Result Register Lo
36 digits wide (144 bits)
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Power6 DFP Multiplication

• Partial products are formed from two multiples to
  reduce area

34 digit multiplication on 36 digit dataflow 1
digit every 2 cycles
16 digit multiplication on dual 18 digit
dataflows 1 digit every cycles
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Performance of Arithemetic Operations
N is the number of digits in the first operand
excluding leading zeros
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Future

• Pipelined Adder with Rounding Injection
• Lia-Kai Wang
• Decimal Multiplication
• Mark Erle and Michael Schulte 32 Counter
• Tomas Lang and A. Nannarelli - 42 Counter
• Alvaro Vazquez et. al. 4221
• Luigi Dadda - counters
• Decimal Multiply-Add Pipeline with Rounding
  Injection
• Divide
• Tomas Lang and A. Nannarelli Base 2 and Base 5
• Intel Format

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Future of Computer Arithmetic

• Is based on clear proofs and expositions of the
  fundamental concepts.
• the easier to understand, the easier to build on
• Arithmetic is very active
• IEEE 754R Standard currently in ballot
• Decimal Floating-Point pipelined designs
• new adder designs, new multiplier designs
• vector processing, image processing, video game

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thanks Stamatis!