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332:437 Lecture 16 FSM Synchronizers

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Material from An Engineering Approach to Digital Design, by ... RET. F/F. Q. Q. SYSCLK(L) RESET(L) ASYN INPUT(L) CATCHING. CELL. SYNCHD INPUT(H) v v. Q(H) ... – PowerPoint PPT presentation

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Title: 332:437 Lecture 16 FSM Synchronizers


1
332437 Lecture 16 FSM Synchronizers
  • Synchronization failure
  • Runt pulses
  • Simple synchronizers
  • Synchronizer timing
  • Handshake interface techniques
  • Summary

Material from An Engineering Approach to Digital
Design, by William I. Fletcher, Englewood Cliffs,
NJ Prentice-Hall
2
Synchronization of Systems
  • Needed when merging independent systems on
    different clocks
  • Problem System controller needs to know when or
    within what time frame it can expect input
    changes from controlled/controlling systems

3
Consequences of Synchronization Failure
  • Input Changes missed by system controller
  • Undefined state transitions occur

4
Input changing Near Triggering Edge of Clock
5
Output Cell in Meta-Stable Condition from Runt
Pulse
6
Meta-Stable Condition of Flip-Flop
7
Example Synchronizer Catching Cell
  • Catching cell converts Pulse into level

8
Synchronizer with Explicit Reset from System
Controller
SYNCHD INPUT(H)
9
Synching Operation of the Pulse-Catching Circuits
10
Synchronizer Timing Considerations
  • May be impractical to increase system clock
    frequency for synchronization
  • Need to instead catch input pulse hold it until
    system controller can service it.
  • fp frequency of input pulse
  • fc Clock frequency
  • tp Period of input pulse
  • tc Period of Clock
  • First assume that fp lt fc

11
Synchronizer Based on These Assumptions
  • tp lt tc So, tp short infrequent in relation
    to system clock
  • State changes of system controller made on rising
    edge of system clock
  • Time period between falling rising edge of
    system clock gt systems setting time

12
Missed Short Asynchronous Input
  • Compared to system clock

13
Level Synchronization When tp gtgt tc
  • Catching level that changes asynchronously with
    respect to system clock
  • Use same circuit as before, but omit catching cell

14
Problem with Asynchronous Inputs
  • Changes in inputs may cause outputs of next state
    decoder to change during set-up hold times of
    flip-flops
  • Causes erratic behavior of present-state register

15
Handshake Interface Technique
  • One party stimulates second party
  • Second party signals first to acknowledge receipt
    of signal
  • First party can now initiate another transaction

16
Handshake Between Systems Operating Asynchronously
17
Problem
  • Internal input changes in one of the systems
    being synchronized can cause transient electrical
    noise on output control lines.
  • May have to design special circuits to sense
    noise transient and delay action until it damps
    out.

18
Summary
  • Synchronization failure
  • Runt pulses
  • Simple synchronizers
  • Synchronizer timing
  • Handshake interface techniques
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