Introduction to Intel IA32 and IA64 Instruction Set Architectures

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Introduction to Intel IA-32 and IA-64 Instruction
Set Architectures
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Dr. Alexey Lugovskoy will be giving a
presentation at 4pm this Thursday (Feb 21) in 499
Dirac. After the presentation there will be a
brief discussion about the new undergraduate
computational biology degree at FSU and Dr.
Lugovskoy will answer questions regarding
opportunities for employment in this field.
Refreshments and pizza will also be provided.
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History
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Recent Intel Processors

• The Intel Pentium 4 Processor Family
  (2000-2006)
• The Intel Xeon Processor (2001-2006)
• The Intel Pentium M Processor (2003-Current)
• The Intel Pentium Processor Extreme Edition
  (2005-2007)
• The Intel Core Duo and Intel Core Solo
  Processors (2006-Current)
• The Intel Xeon Processor 5100 Series and Intel
  Core2 Processor Family (2006-Current)

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History
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Most Recent Intel Processors
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Intel Core 2 Duo Processors
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Intel Core 2 Quad Processors
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Bit and Byte Ordering
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Intel Assembly

• Each instruction is represented by
• Where label presents the line
• A mnemonic is a reserved name for a class of
  instruction opcodes which have the same function.
• The operands argument1, argument2, and argument3
  are optional. There may be from zero to three
  operands, depending on the instruction

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Memory Modes
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Addressing

• The processors use byte addressing
• Intel processors support segmented addressing
• Each address is specified by a segment register
  and byte address within the segment

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Intel Registers
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Basic Program Execution Registers

• General purpose registers
• There are eight registers (note that they are not
  quite general purpose as some instructions assume
  certain registers)
• Segment registers
• They define up to six segment selectors
• EIP register Effective instruction pointer
• EFLAGS Program status and control register

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General Purpose and Segment Registers
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General Purpose Registers

• EAX Accumulator for operands and results data
• EBX Pointer to data in the DS segment
• ECX Counter for string and loop operations
• EDX I/O pointer
• ESI Pointer to data in the segment pointed to
  by the DS register source pointer for string
  operations
• EDI Pointer to data (or destination) in the
  segment pointed to by the ES register
  destination pointer for string operations
• ESP Stack pointer (in the SS segment)
• EBP Pointer to data on the stack (in the SS
  segment)

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Alternative General Purpose Register Names
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Registers in IA-64
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Segment Registers
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Operand Addressing

• Immediate addressing
• Maximum value allowed varies among instructions
  and it can be 8-bit, 16-bit, or 32-bit
• Register addressing
• Register addressing depends on the mode (IA-32 or
  IA-64)

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Register Addressing
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Memory Operand

• Memory operand is specified by a segment and
  offset

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Offset

• Displacement - An 8-, 16-, or 32-bit value.
• Base - The value in a general-purpose register.
• Index The value in a general-purpose register.
• Scale factor A value of 2, 4, or 8 that is
  multiplied by the index value.

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Effective Address
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Effective Address

• Common combinations
• Displacement
• Base
• Base displacement
• (Index scale) displacement
• Base index displacement
• Base (Index scale) displacement

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Addressing Mode Encoding
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Fundamental Data Types
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Example
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Pointer Data Types

• Near pointer
• Far pointer

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128-Bit SIMD Data Types
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BCD Integers

• Intel also supports BCD integers, where each
  digit (0-9) is represented by 4 bits

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Floating Point Numbers
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General Purpose Instructions

• Data transfer instructions

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Data Transfer Instructions
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Data Transfer Instructions
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Binary Arithmetic Instructions
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Decimal Arithmetic Instructions
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Logical Instructions
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Shift and Rotate Instructions
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Bit and Byte Instructions
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Bit and Byte Instructions
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Control Transfer Instructions
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String Instructions
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I/O Instructions

• These instructions move data between the
  processors I/O ports and a register or memory

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Enter and Leave Instructions

• These instructions provide machine-language
  support for procedure calls in block structured
  languages

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Segment Register Instructions

• The segment register instructions allow far
  pointers (segment addresses) to be loaded into
  the segment registers

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Procedure Call Types

• The processor supports procedure calls in the
  following two different ways
• CALL and RET instructions.
• ENTER and LEAVE instructions, in conjunction with
  the CALL and RET instructions

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Stack
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Calling Procedures Using CALL and RET

• Near call (within the current code segment)
• Near return

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Far Call and Far Return

• Far call
• Far return

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Stack During Call and Return
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Parameter Passing

• Passing parameters through the general-purpose
  registers
• Can pass up to six parameters by copying the
  parameters to the general-purpose registers
• Passing parameters on the stack
• Stack can be used to pass a large number of
  parameters and also return a large number of
  values
• Passing parameters in an argument list
• Place the parameters in an argument list
• A pointer to the argument list can then be passed
  to the called procedure

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Saving Procedure State Information

• The processor does not save general purpose
  registers
• A calling procedure should explicitly save the
  values in any of the general-purpose registers
  that it will need when it resumes execution after
  a return
• One can use PUSHA and POPA to save and restore
  all the general purpose registers (except ESP)

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Calls to Other Privilege Levels
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Stack For Calling and Called Procedure
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Procedure Calls For Block-structured Languages

• ENTER and LEAVE instructions automatically create
  and release, respectively, stack frames for
  called procedures
• The ENTER instruction creates a stack frame
  compatible with the scope rules typically used in
  block-structured languages
• The LEAVE instruction, which does not have any
  operands, reverses the action of the previous
  ENTER instruction

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ENTER Instruction
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IA-32 and IA-64 Instruction Format
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Examples of Instruction Formats
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ADD Instructions
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ADD Instructions
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Add Instruction Description
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SCAS/SCASB/SCASW/SCASDScan String
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Next Time

• SSE Instructions
• Brief Introduction to Inline Assembly Programming
• Using gcc