Sin ttulo de diapositiva

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9th Workshop on Electronics for LHC Experiments.
Amsterdam. September 29th - October 3rd, 2003
Fernández-Bedoya C., Marín J., Oller J.C.,
Willmott C.
Http//wwwae.ciemat.es/cms/DTE/Welcome.html
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RO Electronics of the CMS Detector Drift Tube
Chambers
It is part of the electronics of the DT chambers
of CMS muon detector (Readout
Trigger). The aim is the time digitalization and
data transmission to DAQ of the incoming signals
from the Front-End electronics of the
chambers. The first two levels of this data
acquisition system are being developed at CIEMAT
(Madrid, SPAIN)
DT chamber
CMS DETECTOR
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ROB
READ-OUT BOARDS
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Location in the CMS detector
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ROB Time Digitalization
Vdrift cte
t ? x
Time measurement with respect to L1 Accept
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ROB DESIGN PARAMETERS
RATES
40.08 MHz clock 10-34 cm-2s-1 luminosity, at 25
ns bunch crossing. 10 Hz/cm-2 charged particles
rate. L1 Accept reduces to 1 Hz/cm2 of
muons gt 1 KHz/DT chamber cell. 250
DT-chambers, a total of 172,200 anode
channels. Overlapping triggers due to a drift
time of 450 ns. Trigger latency of 3.2 ?s.
100 KHz triggers
neutron fluence 10 years lt 1010cm-2 charged
particles flux lt 10 cm-2s-1 10 year integrated
dose 1 Gy
ENVIRONMENTAL RADIATION
Radiation hard devices are not going to be
employed, radiation tests have to be performed to
every component.
OTHERS
Stray magnetic fields, in the barrel region
around 0.08 Teslas. Limited maintenance for 10
years of operation.
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HPTDC (High Performance Time to Digital Converter)
Developed by the CERN/EP-MIC group, and produced
by IBM in 0.25 ?m CMOS technology.
? 4 registers/channel before L1 buffer. ? 4 L1
buffers of 256 words, each shared by 8
channels. ? Triggers stored in 16 words deep
FIFO. ? 256 words deep readout FIFO.
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HPTDC features
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ROB ARCHITECTURE
READOUT INTERFACE DIAGRAM
4 HPTDC/ROB
Compromise between boards and unused channels.
? Clock synchronous token ring passing scheme
where one TDC is configured as Master. ? Bypass
on error mechanism implemented. ? An Altera FPGA
manages the data_ready/get_data transmission
protocol, slowing down the readout frequency to
20 MHz.
parity)
Serializer
clock
JTAG INTERFACE DIAGRAM
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OTHER ROB FEATURES
Power consumption 2.5 V (0.5A) and 3.3V (0.5A)
4 W. Power supply protection circuitry In case
of 2.5V current consumption over 1.5 A or 3.3V
over 1A, power supply is disconnected, with
powering on cycles every 700 ms (reduces to 10
power consumption). Sensor on board for
temperature, 2.5V and 3.3V voltage and 2.5 V
current monitoring. (Maxim DS2438).
32 bits/HPTDC word Master header and
trailer Error signaling Timing and
positional information ( TDC and
channel). Byte-wise readout (8 bits data1
parity2 byte ID) DS92LV1021 serializer (12 bits
10 data 2 start/stop) at 20 MHz.
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ALTERA CPLD CONTROLLER
Master of the Data_Ready/Get_Data protocol
slowing down readout to 20 MHz. Manages the
channels enabling mechanism for testing chambers
during spill interleaves, simulating artificial
tracks. Triple redundancy registers have been
implemented (solves 1 bit upsets) and a single
event upset counter for radiation tests.
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ROB VALIDATION TESTS
Time resolution 265 ps
Neighbour channels crosstalk Below half HPTDC
bin resolution lt 0.35 ns
Irradiation tests at the Cyclotron Research
Centre (UCL) 51010 p.cm-2 of 60 MeV protons.
SEU MTBFHPTDC 3.8 days in the whole
detector MTBFALTERA 3.4 days in the whole
detector
Test beams at Gamma Irradiation Facility (CERN)
Oct. 01 test beam at GIF. Including a 25 ns
structured beam May. 03 One full Minicrate
operational. No errors found.
TDC can stand high hit rates, including noisy
channels (MHz) and this only affects 1 group of
8 channels.
Temperature cycling
Regulators (lt 5mV/30ºC). 2.5 V current variations
0.4 mA/ºC. Time shift 900ps/70ºC (14ps/ºC). Max
variation 40 ps/ºC. (30 due to
LVDS-TTL receptors).
Lifetime test ROB fully operational at 105ºC
ambient temperature for 4 months (3100 hours).
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MINICRATE
250 Minicrates 1500 ROBs -1440 Rob-128
-60 ROB-32
Power supply 3.3V _at_ 40A 5V _at_ 1.5A
to ROS
MINICRATE
Chamber signals
Link board
RO- Link board
ROBUS




ROB
ROB
CCB
ROB
40 MHz CLOCK
RO-link
TTCSlow control
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ROS
READ-OUT SERVER
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ROS Architecture
Memory
Token ring
Equalizer CLC014AJE
Deserializer DS92LV1212A
FIFO IDT72V243
FPGA
......
X 4
CPLD
event
25 CHANNELS 1 wheel sector
......
X 7
......
GOL
Optical Transmitter
......
X 4
CPLD
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ROS description
9U board located inside racks in towers of the
CMS detector. Its task is the multiplexation of
the data coming from the ROBs of one whole
sector of each wheel.
TOTAL60 ROS 12 ROS/wheel 25
channels/ROS it also accepts trigger data
from the backplane for testing and
synchronisation purposes.
It also has a power supply protection circuit.
A pooling is done by a CPLD every 4 links to
align events and fasten transmission. A token
ring connects all CPLDs for data flow to optical
link management. ROB data format is modified to
include additional information like ROB number
and ROB/ROS link status (transmission errors and
unlocks). 1MB memory for testing and data flow
snapshots for traceability in case of TX errors.
ROB-ROS link 30m copper AC coupled LVDS link
RJ-45 cable from ROBs. Link bandwidth 240
Mbps. Throughput 16Mbps. Measured BER lt 10-15
ROS-DDU link 100m optical link to DDU in USC55
control room. GOL 8B/10B Ethernet Slow (800
Mbps max. Bandwidth) 850 nm VCSEL Honeywell
HFE419x-521 on 62.5/125 ?m multimode fiber LC
conectorized. Link max. Bandwidth 800Mbps.
Throughtput 270Mbps.
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ROS-8 Prototype

• 6U VME board

16Kbytes FIFO per channel. 1Mword deep
memory. Data accessible from VME, stored on
memory or transmitted through 800Mbps copper link.
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ROS-8 Validation Tests
Irradiation tests at the Cyclotron Research
Centre (UCL) 51010 p.cm-2 of 60 MeV protons.
SEU MTBFFIFO 2.3 days in the whole
detector MTBFEQUALIZ 17.2 days in the whole
detector MTBFDESERIALIZER 10.6 days in the
whole detector
May 2003 Test beam at Gamma Irradiation Facility
(CERN) 1 ROS-8 operated in VME mode connected
to 1 Minicrate. No errors found.
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Conclusions
The final architecture of the read-out system for
the CMS drift tube chambers is presented. It
consists on two types of boards ROB for
time digitalization ROS for merging data from
ROBs and transmitting to DDU.
The chosen architecture fulfil the experiment
requirements of trigger and hit rate, radiation
tolerance, limited maintenance and power
consumption among others.