CBM at FAIR

1
CBM at FAIR
New challenges for Front-End Electronics, Data
Acquisition and Trigger Systems

• Walter F.J. Müller, GSI, Darmstadtfor the CBM
  collaboration
• 5th International Conference on Physics
  andAstrophysics of Quark Gluon Plasma, Kolkata,
  India, 8-12 February 2005

2
Outline

• CBM (a short reminder)
• observables
• setup
• FEE/DAQ/Trigger
• requirements
• challenges
• strategies

3
CBM Physics Topics and Observables

• In-medium modifications of hadrons
• ? onset of chiral symmetry restoration at high
  ?B ? measure ?, ?, ? ? ee-
  open charm (D0, D)
• Strangeness in matter
• ? enhanced strangeness production ? measure
  K, ?, ?, ?, ?
• Indications for deconfinement at high ?B
• ? anomalous charmonium suppression ? ?
  measure D0, D
• J/? ? ee-
• Critical point
• ? event-by-event fluctuations
• ? measure p, K

Good e/p separation
Vertex detector
Low cross sections? High interaction rates
Hadron identification
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CBM Setup
? Radiation hard Silicon pixel/strip detectors in
a magnetic dipole field ? Electron detectors
RICH TRD ECAL pion suppression up to 105 ?
Hadron identification RPC, RICH ? Measurement
of photons, p0, ?, and muons ECAL
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Meson Production in central AuAu
W. Cassing, E. Bratkovskaya, A. Sibirtsev, Nucl.
Phys. A 691 (2001) 745
SIS100/ 300
10 MHz interaction rateneeded for 10-15 A GeV
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Open Charm Detection
Some hadronic decay modes D0 (c? 124.4 ?m) D0
? K-? (3.9 ? 0.09) D? (c? 317 ?m) D ?
K-?? (9 ? 0.6)
AuAu _at_ 25 AGeV D0 decays
Measure displaced vertexwith resolution of 100 µm
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A Typical AuAu Collision
Central AuAu collision at 25 AGeV URQMD
GEANT4 160 p 170 n 360 ?-
330 ? 360 ?0 41 K 13 K-
42 K0

• ? 107 AuAu interactions/sec
• (up to 109 ions/sec, 1 target)
• ? high particle flux and fluence in detectors
• ? selective triggers needed

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Detector Requirements
Hit rates for 107 minimum bias AuAu collisions
at 25 AGeV
Rates of gt 10 kHz/cm2 in large part of detectors
! ? main thrust of our detector design
studies ? typical detector element count rate
100 kHz
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Trigger Requirements
assume archive rate few GB/sec 20 kevents/sec

• In-medium modifications of hadrons
• ? onset of chiral symmetry restoration at high
  ?B ? measure ?, ?, ? ? ee-
  open charm (D0, D)
• Strangeness in matter
• ? enhanced strangeness production ? measure
  K, ?, ?, ?, ?
• Indications for deconfinement at high ?B
• ? anomalous charmonium suppression ? ?
  measure D0, D -
• J/? ? ee
• Critical point
• ? event-by-event fluctuations
• ? measure p, K

offline
trigger
trigger ondisplaced vertex
offline
drives FEE/DAQarchitecture
trigger
trigger
trigger on high pt e - e- pair
offline
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CBM DAQ Requirements Profile

• D and J/? signal drives the rate capability
  requirements
• D signal drives FEE and DAQ/Trigger requirements
• Problem similar to B detection, see BTeV, LHCb
• Adopted approach
• displaced vertex 'trigger' in first level, like
  in BTeV
• Additional Problem
• DC beam ? interactions at random times
• ? time stamps with ns precision needed
• ? explicit event association needed
• Current design for FEE and DAQ/Trigger
• Self-triggered FEE
• Data-push architecture

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Conventional FEE-DAQ-Trigger Layout
Especially instrumented detectors
Detector
L0 Trigger
fbunch
Trigger Primitives
Dedicated connections
FEE
Cave
Limited capacity
Shack
L1 Accept
DAQ
Modest bandwidth
L2 Trigger
L1 Trigger
Limited L1 trigger latency
Specialized trigger hardware
Standard hardware
Archive
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Limits of Conventional Architecture
Decision time for first level trigger
limited. typ. max. latency 4 µs for LHC
Not suitable for complex global triggers like
secondary vertex search
Only especially instrumented detectors can
contribute to first level trigger
Limits future trigger development
Large variety of very specific trigger hardware
High development cost
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The way out .. use Data Push Architecture
Especially instrumented detectors
Detector
L0 Trigger
fbunch
Trigger Primitives
fclock
Dedicated connections
FEE
Timedistribution
Cave
Limited capacity
Shack
L1 Accept
DAQ
High bandwidth
Modest bandwidth
L1 Trigger
Limited L1 trigger latency
Specialized trigger hardware
Special hardware
Standard hardware
Archive
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The way out ... use Data Push Architecture
Detector
fclock
FEE
Cave
Shack
DAQ
High bandwidth
Special hardware
Archive
15
The way out ... use Data Push Architecture
Detector
Self-triggered front-end Autonomous hit detection
fclock
FEE
No dedicated trigger connectivity All detectors
can contribute to L1
Cave
Shack
DAQ
Large buffer depth available System is
throughput-limited and not latency-limited
High bandwidth
Modular design Few multi-purpose rather many
special-purpose modules
Special hardware
Archive
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Toward Multi-Purpose FEE Chain
preFilter
digital Filter
Hit Finder
Backend Driver
PreAmp
ADC

• Pad
• GEM's
• PMT
• APD's

Anti-AliasingFilter
Sample rate 10-100 MHz Dyn. range 8...12 bit
'Shaping' 1/t Tailcancellation Baselinerestorer
Hit parameter estimators Amplitude Time
Clustering Buffering Link protocol
All potentially in one mixed-signal chip
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CBM DAQ and Online Event Selection
Data flow 1 TB/sec
Gilder helps
Moore helps
1st level selection 1015 operation/sec
Data flow few 10 GB/sec
to archive few 1 GB/sec
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L1 Event Selection Farm Layout

• Use programmable logic for cores of algorithms
• Use high-speed SoC processors (look beyond PC's)
• Use serial connection fabric (links and switches)
• Modular design (only few board types)

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CPU and FPGA Destined to Merge

• Example Stretch S5xxx
• at first glance looks like yetanother CPU with a
  SIMD extension, like MMX

• The innovation
• configurable instruction set
• compiler generates new instructions and the code
  which uses them

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CBM FEE/DAQ Summary
Substantial RD needed

• Self-triggered FEE
• autonomous hit detection, time-stamping with ns
  presision
• sparsification, hit buffering, high output
  bandwidth
• High bandwidth event building network
• to cope with few 100 MHz interaction rate in p-p,
  p-A
• likely be done in time slices or event slices
• L1 processor farm
• feasible with PC FPGA Moore (needed 2014)
• but look beyond todays PC's
• Efficient algorithms (109 tracks/sec)

Quitedifferentfrom thecurrentLHC
styleelectronics
This is FutureDAQ
Part of an EU FP6 project, togetherwith
PANDAand COMPASS
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CBM Collaboration 39 institutions, 14
countries
China Hua-Zhong Univ., Wuhan Croatia RBI,
Zagreb Cyprus Nikosia Univ. Czech
Republic Czech Acad. Science, Rez Techn. Univ.
Prague   France IReS Strasbourg Germany
Univ. Heidelberg, Phys. Inst. Univ. HD,
Kirchhoff Inst. Univ. Frankfurt Univ.
Kaiserslautern Univ. Mannheim Univ.
Marburg Univ. Münster FZ Rossendorf GSI Darmstadt
Russia CKBM, St. Petersburg IHEP Protvino INR
Troitzk ITEP Moscow KRI, St. Petersburg Kurchatov
Inst., Moscow LHE, JINR Dubna LPP, JINR
Dubna LIT, JINR Dubna LTP, JINR Dubna MEPhi,
Moskau Obninsk State Univ. PNPI Gatchina SINP,
Moscow State Univ. St. Petersburg Polytec.
U. Spain Santiago de Compostela Uni.
Ukraine Shevshenko Univ. , Kiev
Hungaria KFKI Budapest Eötvös Univ.
Budapest Korea Korea Univ. Seoul Pusan National
Univ. Norway Univ. Bergen Poland Krakow
Univ. Warsaw Univ. Silesia Univ.
Katowice   Portugal LIP Coimbra Romania NIPNE
Bucharest
membership applications in italic