Motivation and Design Issues

1
Motivation and Design Issues

• Interest in exhibiting advantage of CMOS based
  digital control
• Very low standby power feasible in PFM (low
  power) mode
• Dramatic power saving in PWM mode due to internal
  power management

2
System Block Diagram
REF

• Two modes PWM and PFM

3
Berkeley Switcher Specifications
4
Power Train

• Problem high input voltage vs low voltage
  process
• Solutions
• 1. Cascoded stucture
• 2. Lateral drain extension structure

5
Power Train Cascoded Structure
Working voltage 2.5V
6
Power Train LDD Structure
p-LDD layout
Rdson
Measured break down voltage
n-LDD layout
p-LDD 6.57.2V
n-LDD 7.58V
ID (mA)
ID (mA)
VDS (V)
VDS (V)
7
Cascoded Structure Test Results
Rdson
Rdson
SW
NMOS break down voltage 7.7V
PMOS break down voltage 7.9V
ID (uA)
VDS (V)
8
Internal Power Management

• Scavenges power from gate drive discharge
• Offers safe supply voltage for controller
  circuitry

9
Internal Voltage Regulations

• Total current consumptions 1?A
• BW of each amplifier 40kHz

10
Control Law

• PFM Mode (low power, low quiescent curr.)
• Fixed on-time control ? avoids ripple jitter due
  to discrete sampling of comparators at rising
  Vout in hyst ctrl
• ton 0.8 Tsw 1.33 ?s ? Vripp,max 90 mV _at_
  Vin 5.5 V, Iout 0.1 mA
• At high output loads, still jitter due to
  sampling
• PWM Mode
• PID control with digital dither
• Saturated controller response (for large
  transients)

11
PFM (Fixed On-time) Mode
12
ADC and DPWM Resolution

• ?VADC 16 mV ? 0.8 reg _at_ Vout 1V
• ?VDPWM 5.4 mV _at_ Vin 5.5 V
• 5 bit ring osc 5 bit digital dither
• no limit cycling in steady state
• Sampled at fsw

13
PWM Mode DPWM Module
14
Protection Mode ? Soft Start

• Build into digital control loop
• Disable PD control
• Make error signal slew the digital integrator to
  the appropriate level corresponding to Vout
  Vref
• Gain of error signal set to effect desired
  duration of soft-start sequence, tsoft-start
  1100 ?s

15
Digital processing core
Int
Fully on
From ringADC
Dc
De
Dc_calc
PD
Go to DPWM
Dither
Fully off
Clamp
16
Ring ADC Basics

• Frequency of ring oscillator has linear relation
  with Itot when voltage swing is below threshold

17
Ring ADC Architecture
Sampling freq500kHz, LSB16mV, approx 100mV
window, VDD1.5V Measured current 36.72?A, area
0.15 mm2
18
PFM Mode Comparator Details
19
PFM Mode Quiescent Current

• Simulation 600kHz sampling frequency
• Comparator, ring osc., level shifters(from ring
  voltage to internal VDD), and clock generation
  3µA (from PVIN/2)
• Internal voltage regulators 1.0µA(from PVIN)

20
Berkeley Switcher Layout
21
Comparison between Analog and Digital Controllers

• For mobile phone application

22
Berkeley Switcher Pin Description

• Taped-out in Oct 10, 2002, packaged chip
  returned Jan.20, 2003
• Implemented in 0.25um CMOS

23
Personnel and Roles

• Prof. Seth Sanders, project leader
• Jinwen Xiao, PhD student (5th year), leadership
  on IC designs
• Angel Peterchev, PhD student (4rd year),
  leadership on architecture issues
• Kenny (Jianhui) Zhang, PhD student (2nd year),
  responsibility for power train design

24
Thanks To

• Y.C. Liang, visiting Nov.2001Sep.2002 from
  Natl. Univ. Singapore, for advising on power
  train design
• Joe Emlano for packaging the chip