Mixed Style RTL Modeling

1
Mixed Style RTL Modeling
ECE 545 Lecture 6
2
Structural Modeling Generate Statements Examples
3
Example 1
4
A 4-to-1 Multiplexer

• LIBRARY ieee
• USE ieee.std_logic_1164.all
• ENTITY mux4to1 IS
• PORT ( w0, w1, w2, w3 IN STD_LOGIC
• s IN STD_LOGIC_VECTOR(1 DOWNTO 0)
• f OUT STD_LOGIC )
• END mux4to1
• ARCHITECTURE Dataflow OF mux4to1 IS
• BEGIN
• WITH s SELECT
• f lt w0 WHEN "00",
• w1 WHEN "01",
• w2 WHEN "10",
• w3 WHEN OTHERS
• END Dataflow

5
Straightforward code for Example 1

• LIBRARY ieee
• USE ieee.std_logic_1164.all
• ENTITY Example1 IS
• PORT ( w IN STD_LOGIC_VECTOR(0 TO 15)
• s IN STD_LOGIC_VECTOR(3 DOWNTO 0)
• f OUT STD_LOGIC )
• END Example1

6
Straightforward code for Example 1

• ARCHITECTURE Structure OF Example1 IS
• COMPONENT mux4to1
• PORT ( w0, w1, w2, w3 IN STD_LOGIC
• s IN STD_LOGIC_VECTOR(1 DOWNTO 0)
• f OUT STD_LOGIC )
• END COMPONENT
• SIGNAL m STD_LOGIC_VECTOR(0 TO 3)
• BEGIN
• Mux1 mux4to1 PORT MAP ( w(0), w(1), w(2),
  w(3), s(1 DOWNTO 0), m(0) )
• Mux2 mux4to1 PORT MAP ( w(4), w(5), w(6),
  w(7), s(1 DOWNTO 0), m(1) )
• Mux3 mux4to1 PORT MAP ( w(8), w(9),
  w(10), w(11), s(1 DOWNTO 0), m(2) )
• Mux4 mux4to1 PORT MAP ( w(12), w(13), w(14),
  w(15), s(1 DOWNTO 0), m(3) )
• Mux5 mux4to1 PORT MAP ( m(0), m(1), m(2),
  m(3), s(3 DOWNTO 2), f )
• END Structure

7
Modified code for Example 1

• ARCHITECTURE Structure OF Example1 IS
• COMPONENT mux4to1
• PORT ( w0, w1, w2, w3 IN STD_LOGIC
• s IN STD_LOGIC_VECTOR(1 DOWNTO 0)
• f OUT STD_LOGIC )
• END COMPONENT
• SIGNAL m STD_LOGIC_VECTOR(0 TO 3)
• BEGIN
• G1 FOR i IN 0 TO 3 GENERATE
• Muxes mux4to1 PORT MAP (
• w(4i), w(4i1), w(4i2), w(4i3), s(1
  DOWNTO 0), m(i) )
• END GENERATE
• Mux5 mux4to1 PORT MAP ( m(0), m(1), m(2), m(3),
  s(3 DOWNTO 2), f )
• END Structure

8
Example 2
w
y
w
y
0
0
0
0
y
w
w
y
1
1
1
1
y
y
2
2
y
y
En
3
3
w
y
y
0
0
4
w
y
y
1
1
5
y
y
2
6
w
w
y
y
y
2
En
3
0
0
7
w
y
w
1
1
3
y
2
w
y
y
w
y
En
En
8
0
0
3
w
y
y
1
1
9
y
y
2
10
y
y
En
3
11
y
w
y
0
0
12
y
w
y
1
1
13
y
y
2
14
y
y
En
3
15
9
A 2-to-4 binary decoder

• LIBRARY ieee
• USE ieee.std_logic_1164.all
• ENTITY dec2to4 IS
• PORT ( w IN STD_LOGIC_VECTOR(1 DOWNTO 0)
• En IN STD_LOGIC
• y OUT STD_LOGIC_VECTOR(0 TO 3) )
• END dec2to4
• ARCHITECTURE Dataflow OF dec2to4 IS
• SIGNAL Enw STD_LOGIC_VECTOR(2 DOWNTO 0)
• BEGIN
• Enw lt En w
• WITH Enw SELECT
• y lt "1000" WHEN "100",
• "0100" WHEN "101",
• "0010" WHEN "110",
• "0001" WHEN "111",
• "0000" WHEN OTHERS

10
VHDL code for Example 2 (1)

• LIBRARY ieee
• USE ieee.std_logic_1164.all
• ENTITY dec4to16 IS
• PORT (w IN STD_LOGIC_VECTOR(3 DOWNTO 0)
• En IN STD_LOGIC
• y OUT STD_LOGIC_VECTOR(0 TO 15) )
• END dec4to16

11
VHDL code for Example 2 (2)

• ARCHITECTURE Structure OF dec4to16 IS
• COMPONENT dec2to4
• PORT ( w IN STD_LOGIC_VECTOR(1 DOWNTO 0)
• En IN STD_LOGIC
• y OUT STD_LOGIC_VECTOR(0 TO 3) )
• END COMPONENT
• SIGNAL m STD_LOGIC_VECTOR(0 TO 3)
• BEGIN
• G1 FOR i IN 0 TO 3 GENERATE
• Dec_ri dec2to4 PORT MAP ( w(1 DOWNTO 0), m(i),
  y(4i TO 4i3) )
• G2 IF i3 GENERATE
• Dec_left dec2to4 PORT MAP ( w(i DOWNTO i-1),
  En, m )
• END GENERATE
• END GENERATE
• END Structure

12
Mixed Modeling Example
13
Mixed Style Modeling

• architecture ARCHITECTURE_NAME of ENTITY_NAME is
• Here you can declare signals, constants,
  functions, procedures
• Component declarations
• No variable declarations !!
• begin
• Concurrent statements
• Concurrent simple signal assignment
• Conditional signal assignment
• Selected signal assignment
• Generate statement
• Component instantiation statement
• Process statement
• inside process you can use only sequential
  statements
• end ARCHITECTURE_NAME

14
Simple Processor
15
N-bit register with enable

• LIBRARY ieee
• USE ieee.std_logic_1164.all
• ENTITY regn IS
• GENERIC ( N INTEGER 8 )
• PORT ( D IN STD_LOGIC_VECTOR(N-1 DOWNTO 0)
• En IN STD_LOGIC
• Clock IN STD_LOGIC
• Q OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) )
  
• END regn
• ARCHITECTURE Behavior OF regn IS
• BEGIN
• PROCESS
• BEGIN
• IF (Clock'EVENT AND Clock '1) THEN
• IF En '1' THEN
• Q lt D
• END IF

16
N-bit tristate buffer

• LIBRARY ieee
• USE ieee.std_logic_1164.all
• ENTITY trin IS
• GENERIC ( N INTEGER 8 )
• PORT ( X IN STD_LOGIC_VECTOR(N-1 DOWNTO 0)
• En IN STD_LOGIC
• Y OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) )
• END trin
• ARCHITECTURE Behavior OF trin IS
• BEGIN
• Y lt (OTHERS gt 'Z') WHEN En '0' ELSE X
• END Behavior

17
Packages and component declarations

• LIBRARY ieee
• USE ieee.std_logic_1164.all
• PACKAGE exec_components IS
• COMPONENT regn -- register
• GENERIC ( N INTEGER 8 )
• PORT ( D IN STD_LOGIC_VECTOR(N-1 DOWNTO 0)
  
• En IN STD_LOGIC
• Clock IN STD_LOGIC
• Q OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) )
• END COMPONENT
• COMPONENT trin -- tri-state buffers
• GENERIC ( N INTEGER 8 )
• PORT ( X IN STD_LOGIC_VECTOR(N-1 DOWNTO 0)
  
• En IN STD_LOGIC
• Y OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) )
• END COMPONENT

18
Processor Execution Unit (1)

• LIBRARY ieee
• USE ieee.std_logic_1164.all
• USE work.exec_components.all
• USE ieee.std_logic_signed.all
• ENTITY Proc_Exec IS
• PORT ( Data IN STD_LOGIC_VECTOR(7 DOWNTO
  0)
• Clock IN STD_LOGIC Rin IN
  STD_LOGIC_VECTOR(0 to 3)
• Rout IN STD_LOGIC_VECTOR(0 to 3)
• Ain IN STD_LOGIC
• Gin IN STD_LOGIC
• Gout IN STD_LOGIC AddSub IN
  STD_LOGIC
• Extern IN STD_LOGIC
• BusWires INOUT STD_LOGIC_VECTOR(7 DOWNTO
  0)
• END Proc_Exec

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Processor Execution Unit (2)

• ARCHITECTURE Mixed OF Proc_Exec IS
• TYPE RegArray is ARRAY(0 to 3) of
  STD_LOGIC_VECTOR(7 downto 0)
• SIGNAL R RegArray
• SIGNAL A STD_LOGIC_VECTOR(7 DOWNTO 0)
• SIGNAL G STD_LOGIC_VECTOR(7 DOWNTO 0)
• SIGNAL Sum STD_LOGIC_VECTOR(7 DOWNTO 0)

20
Processor Execution Unit (3)

• BEGIN
• G1 FOR i IN 0 TO 3 GENERATE
• Regs regn PORT MAP (
• D gt BusWires,
• En gt Rin(i),
• Clock gt Clock,
• Q gt R(i))
• Trins trin PORT MAP (
• X gt R(i),
• En gt Rout(i),
• Y gt BusWires)
• END GENERATE

21
Processor Execution Unit (4)

• RegA regn PORT MAP (
• D gt BusWires,
• En gt Ain,
• Clock gt Clock,
• Q gt A)
• RegG regn PORT MAP (
• D gt Sum,
• En gt Gin,
• Clock gt Clock,
• Q gt G)
• triG trin PORT MAP (
• X gt G,
• En gt Gout,
• Y gt BusWires)

22
Processor Execution Unit (5)

• ALU WITH AddSub Select
• Sum lt A B WHEN 0,
• A B WHEN OTHERS
• Tri_extern trin PORT MAP (
• X gt Data,
• En gt Extern,
• Y gt BusWires)
• END Mixed

23
Processor Control Unit (1)

• LIBRARY ieee
• USE ieee.std_logic_1164.all
• USE work.control_components.all
• ENTITY Proc_Control IS
• PORT ( Func IN STD_LOGIC_VECTOR(1 TO 6)
• w IN STD_LOGIC
• Clock IN STD_LOGIC Reset
  IN STD_LOGIC
• Rin OUT STD_LOGIC_VECTOR(0 to 3)
• Rout OUT STD_LOGIC_VECTOR(0 to 3)
• Ain OUT STD_LOGIC
• Gin OUT STD_LOGIC
• Gout OUT STD_LOGIC AddSub OUT
  STD_LOGIC
• Extern OUT STD_LOGIC
• Done OUT STD_LOGIC
• END Proc_Control

24
Processor Instructions
25
Processor
26
Counter of instruction clock cycles
T
T
T
T
1
2
3
0
y
y
y
y
0
1
2
3
2-to-4 decoder
w
w
En
0
1
Count
1
Q
Q
1
0
Clock
Up-counter
Clear
Reset
27
The Function Register and Decoders
X
X
X
X
Y
Y
Y
Y
I
I
I
I
0
1
2
3
0
1
2
3
0
1
2
3
y
y
y
y
y
y
y
y
y
y
y
y
0
1
2
3
0
1
2
3
0
1
2
3
2-to-4 decoder
2-to-4 decoder
2-to-4 decoder
w
w
w
w
w
w
En
En
En
0
1
0
1
0
1
1
1
1
Clock
Function Register
FR
in
f
f
Rx
Rx
Ry
Ry
1
0
1
0
1
0
Function
28
Control signals asserted in each operation and
time step
29
Packages and component declarations

• LIBRARY ieee
• USE ieee.std_logic_1164.all
• PACKAGE control_components IS
• COMPONENT dec2to4
• PORT (w IN STD_LOGIC_VECTOR(1 DOWNTO 0)
• En IN STD_LOGIC
• y OUT STD_LOGIC_VECTOR(0 TO 3)
  )
• END COMPONENT
• COMPONENT upcount
• GENERIC ( N INTEGER 2 )
• PORT ( Clock IN STD_LOGIC
• Reset IN STD_LOGIC
• Q OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) )
• END COMPONENT
• END control_components

30
N-bit Up Counter (1)

• LIBRARY ieee
• USE ieee.std_logic_1164.all
• USE ieee.std_logic_unsigned.all
• ENTITY upcount IS
• GENERIC ( N INTEGER 2 )
• PORT (Clock IN STD_LOGIC
• Reset IN STD_LOGIC
• Q BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO 0) )
  
• END upcount

31
N-bit Up Counter (2)

• ARCHITECTURE Behavior OF upcount IS
• BEGIN
• upcount PROCESS ( Clock )
• BEGIN
• IF (Clock'EVENT AND Clock '1') THEN
• IF Reset '1' THEN
• Q lt (OTHERS gt 0)
• ELSE
• Q lt Q 1
• END IF
• END IF
• END PROCESS
• END Behavior

32
Processor Control Unit (2)

• ARCHITECTURE Mixed OF Proc_Control IS
• SIGNAL Clear STD_LOGIC
• SIGNAL Count STD_LOGIC_VECTOR(1 DOWNTO 0)
• SIGNAL T STD_LOGIC_VECTOR(0 TO 3)
• SIGNAL FRin STD_LOGIC
• SIGNAL FuncReg IN STD_LOGIC_VECTOR(5 DOWNTO
  0)
• SIGNAL I STD_LOGIC_VECTOR(0 TO 3)
• SIGNAL X STD_LOGIC_VECTOR(0 TO 3)
• SIGNAL Y STD_LOGIC_VECTOR(0 TO 3)
• SIGNAL High STD_LOGIC

33
Counter of instruction clock cycles
T
T
T
T
1
2
3
0
y
y
y
y
0
1
2
3
2-to-4 decoder
w
w
En
0
1
Count
1
Q
Q
1
0
Clock
Up-counter
Clear
Reset
34
Processor Control Unit (3)

• BEGIN
• counter upcount PORT MAP (
• Clock gt Clock,
• Reset gt Clear,
• Q gt Count )
• Clear lt Reset OR Done OR (NOT w AND T(0))
• High lt '1'
• decT dec2to4 PORT MAP (
• w gt Count,
• En gt High,
• y gt T )

35
The Function Register and Decoders
X
X
X
X
Y
Y
Y
Y
I
I
I
I
0
1
2
3
0
1
2
3
0
1
2
3
y
y
y
y
y
y
y
y
y
y
y
y
0
1
2
3
0
1
2
3
0
1
2
3
2-to-4 decoder
2-to-4 decoder
2-to-4 decoder
w
w
w
w
w
w
En
En
En
0
1
0
1
0
1
1
1
1
Clock
Function Register
FR
in
f
f
Rx
Rx
Ry
Ry
1
0
1
0
1
0
Function
36
Processor Control Unit (4)

• functionreg regn GENERIC MAP ( N gt 6 )
• PORT MAP (
• D gt Func,
• En gt FRin,
• Clock gt Clock,
• Q gt FuncReg )
• FRin lt w AND T(0)
• decI dec2to4 PORT MAP (
• w gtFuncReg(5 DOWNTO
  4),
• En gt High,
• y gt I )

37
Processor Control Unit (5)

• decX dec2to4 PORT MAP (
• w gt FuncReg(3
  DOWNTO 2),
• En gt High,
• y gt X )
• decY dec2to4 PORT MAP (
• w gt FuncReg(1
  DOWNTO 0),
• En gt High,
• y gt Y )

38
Control signals asserted in each operation and
time step
39
Processor Control Unit (5)

• control_signals PROCESS (T, I, X, Y)
• BEGIN
• Extern lt '0' Done lt '0' Ain lt '0' Gin
  lt '0'
• Gout lt '0' AddSub lt '0' Rin lt "0000"
  Rout lt "0000"
• CASE T IS
• WHEN 1000 gt null --
  no signals asserted in the time step T0
• WHEN 0100 gt
• CASE I IS
• WHEN 1000" gt -- Load
• Extern lt '1' Rin lt X Done lt '1'
• WHEN "0100" gt -- Move
• Rout lt Y Rin lt X Done lt '1'
• WHEN OTHERS gt -- Add, Sub
• Rout lt X Ain lt '1'
• END CASE
• END PROCESS

40
Processor Control Unit (6)

• WHEN 0010 gt
• CASE I IS
• WHEN 0010" gt -- Add
• Rout lt Y Gin lt '1'
• WHEN 0001" gt -- Sub
• Rout lt Y AddSub lt '1' Gin lt '1'
• WHEN OTHERS gt -- Load, Move
• END CASE
• WHEN OTHERS gt -- define signals asserted in
  time step T3
• CASE I IS
• WHEN 1000" gt -- Load
• WHEN "0100" gt -- Move
• WHEN OTHERS gt -- Add, Sub
• Gout lt '1' Rin lt X Done lt '1'
• END CASE
• END CASE

41
Processor Control Unit (7)

• END PROCESS
• END Mixed

42
Using Arrays of Test Vectors In Testbenches
43
Testbench (1)

• LIBRARY ieee
• USE ieee.std_logic_1164.all
• ENTITY sevenSegmentTB is
• END sevenSegmentTB
• ARCHITECTURE testbench OF sevenSegmentTB IS
• COMPONENTsevenSegment PORT (
• bcdInputs IN STD_LOGIC_VECTOR (3 DOWNTO 0)
• seven_seg_outputs OUT STD_LOGIC_VECTOR(6
  DOWNTO 0)
• )
• end COMPONENT
• CONSTANT PropDelay time 40 ns
• CONSTANT SimLoopDelay time 10 ns

44
Testbench (2)

• TYPE vector IS RECORD
• bcdStimulus STD_LOGIC_VECTOR(3 downto 0)
• sevSegOut STD_LOGIC_VECTOR(6 downto 0)
• END RECORD
• CONSTANT NumVectors INTEGER 10
• TYPE vectorArray is ARRAY (0 TO NumVectors - 1)
  OF vector
• CONSTANT vectorTable vectorArray (
• (bcdStimulus gt "0000", sevSegOut gt
  "0000001"),
• (bcdStimulus gt "0001", sevSegOut gt
  "1001111"),
• (bcdStimulus gt "0010", sevSegOut gt
  "0010010"),
• (bcdStimulus gt "0011", sevSegOut gt
  "0000110"),
• (bcdStimulus gt "0100", sevSegOut gt
  "1001100"),
• (bcdStimulus gt "0101", sevSegOut gt
  "0100100"),
• (bcdStimulus gt "0110", sevSegOut gt
  "0100000"),
• (bcdStimulus gt "0111", sevSegOut gt
  "0001111"),
• (bcdStimulus gt "1000", sevSegOut gt
  "0000000"),

45
Testbench (3)

• SIGNAL StimInputs STD_LOGIC_VECTOR(3 downto 0)
• SIGNAL CaptureOutputs STD_LOGIC_VECTOR(6 downto
  0)
• BEGIN
• u1 sevenSegment PORT MAP (
• bcdInputs gt StimInputs,
• seven_seg_outputs gt CaptureOutputs)

46
Testbench (4)

• LoopStim PROCESS
• BEGIN
• FOR i in 0 TO NumVectors-1 LOOP
• StimInputs lt vectorTable(i).bcdStimulus
• WAIT FOR PropDelay
• ASSERT CaptureOutputs vectorTable(i).sevSeg
  Out
• REPORT Incorrect Output
• SEVERITY error
• WAIT FOR SimLoopDelay
• END LOOP

47
Testbench (5)

• WAIT
• END PROCESS
• END testbench