Chapter 2 Computer System Overview

1
Chapter 2Computer System Overview
2
Outline

• Basic Elements
• Processor Registers
• Instruction Execution
• Interrupts
• I/O Structure
• Storage Hierarchy
• Hardware Protection
• Network Structure

3
Overview

• An Operating System makes the computing power
  available to users by controlling the hardware
• Let us review the aspects of computer hardware
  which are important for the OS

4
Basic Elements
5
Basic Elements (Cont.)

• Processor (CPU)
• Device Controller (I/O Module)
• Hardware (with registers called I/O ports) that
  moves data between CPU and peripherals
• Each is in charge of a specific type of device
• Bus provide access to shared memory
• Main Memory hold data and code
• CPU and device controllers can execute
  concurrently, competing for memory cycles
• Memory controller synchronize access to the
  memory

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Basic Elements (Cont.)
Address
Data
7
I/O Module Structure
I/O Address
Command, Interrupt
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I/O Module Structure (Cont.)

• Data to/from system bus are buffered in data
  registers
• Status/Control registers hold
• current status information of the I/O operation
• current control information from CPU
• I/O logic interact with CPU via control lines
• Contains logic specific to the interface of each
  device

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CPU Registers (fast memory on CPU)

• Control Status Registers
• Generally not available to user programs
• Some used by CPU to control its operation
• Some used by OS to control program execution
• User-visible Registers
• Available to system (OS) and user programs
• Holds data, addresses, and some condition codes

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Examples of Control Status Registers

• Program Counter (PC) Contains the address of the
  next instruction to be fetched
• Instruction Register (IR) Contains the
  instruction most recently fetched
• Program Status Word (PSW)
• Condition codes and status info bits (like
  Interrupt enable/disable bit, supervisor(OS)/user
  mode bit)
• MAR, MBR, I/O AR, I/O BR
• Interrupt registers, system stack pointer, memory
  management hardware

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User-Visible Registers

• Data Registers
• Can be assigned by the user program to perform
  operations on data
• Address Registers
• Contain memory address of data and instructions
• May contain a portion of an address that is used
  to calculate the complete address
• Examples of Address Registers
• Index/Offset register involves adding an index
  to a base value to get an address
• Segment pointer when memory is divided into
  segments, memory is referenced by a segment and
  an offset
• Stack pointer points to top of stack

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User-Visible Registers (Cont.)

• Condition Codes or Flags
• Bits set by the processor hardware as a result of
  operations
• Can be accessed by a program but not changed
  directly
• Examples
• sign flag
• zero flag
• overflow flag

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Instruction Execution
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Basic Instruction Cycle
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Basic Instruction Cycle (Cont.)

• The CPU fetches the next instruction (with
  operands) from memory.
• Program counter (PC) holds address of the
  instruction to be fetched next
• Program counter is automatically incremented
  after each fetch (unless a jump command)
• The fetched command is loaded into Instruction
  register (IR)
• Then the CPU executes the instruction
• Processor-memory
• Processor-I/O
• Data processing
• Control

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Example of Program Execution

• Command
• 1 Load AC from Memory
• 2 Store AC to memory
• 5 Add to AC from memory
• Add the contents of memory 940 to the content of
  memory 941 and stores the result at 941

Fetch
Execution
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Interrupts
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Overview

• Interrupt a mechanism by which other modules
  may interrupt the normal processing of CPU
• Improving processing efficiency -- especially for
  I/O
• Typically initiated by a hardware device
• Asynchronously to the currently executing process
• A trap is a software-generated interrupt caused
  either by an error or a user request
• Occur as a result of the current executing
  process
• Divided-by-zero error, memory page fault
• Most modern operating systems are interrupt driven

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Overview (Cont.)

• Classes of interrupts
• Program -- Arithmetic overflow, division by zero,
  illegal memory access
• Timer -- Allow processor to perform certain
  functions on a regular basis
• I/O -- Normal completion of operations, error
  condition
• Hardware failure -- Power failure, memory parity
  error

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CPU Must Wait for I/O to Complete -- If No
Interrupt Mechanism

• WRITE transfer control to the printer driver (I/O
  pgm)
• I/O pgm prepare I/O module for printing (4)
• CPU has to WAIT for I/O command (actual I/O to
  complete)
• Long wait for a printer
• I/O pgm finishes in (5) and report status of
  operation

Printer
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Interrupts Improve CPU Usage

• WRITE transfer control to the printer driver (I/O
  pgm)
• I/O pgm prepare I/O module and issues the I/O
  command (4)
• I/O pgm branches to user pgm
• User code gets executed during I/O operation no
  waiting
• User pgm gets interrupted (x) when I/O operation
  is done and branches to interrupt handler to
  examine status of I/O module
• Execution of user code resumes

Printer
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Interrupt Time Line for A Single Process Doing
Output
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Transfer of Control via Interrupts
User Program
Interrupt Handler
1
Interrupt occurs here
i
i1
M
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Instruction Cycle with Interrupts
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Instruction Cycle with Interrupts (Cont.)

• CPU checks for interrupts after each instruction
• Determines which type of interrupt has occurred
• polling
• vectored interrupt system
• If no interrupts, then fetch the next instruction
  for the current program
• If an interrupt is pending, then suspend
  execution of the current program, and execute the
  interrupt handler

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Vectored Interrupt System
1
2
OOXXO
OOXXO
M
Interrupt M occurs
Solaris
Interrupt Handler
iv_handler iv_arg iv_pil iv_pending
Kernel Memory
ddi_add_intr(), ddi_add_softintr()
iv_mutex
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Interrupt Handler

• A program that determines nature of the interrupt
  and performs whatever actions are needed
• Control is transferred to this program
• Control must be transferred back to the
  interrupted program so that it can be resumed
  from the point of interruption
• This point of interruption can occur anywhere in
  the program
• Thus must save the state of the program (content
  of PC PSW registers ...)

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Simple Interrupt Processing
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Changes in Memory and Registers for an Interrupt
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Changes in Memory and Registers for an Interrupt
(Cont.)
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Interrupts And Multiprogramming

• Not like printingWhen a program reads a value on
  a I/O device it will need to wait for the I/O
  operation to complete
• Interrupts are mostly effective when a single CPU
  is shared among several concurrently active
  processes.
• The CPU can then switch to execute another
  program when a program waits for the result of
  the read operation. (more later)

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Interrupts And Multiprogramming (Cont.)
User Program 1
I/O Program
1
2
READ
READ
I/O Command
Interrupt Handler
User Program 2
4
3
End
READ
READ
Which process is the next running process after
the interrupt handler finishes? ? Depend on CPU
scheduling policy
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I/O Communication Techniques
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Two I/O Methods

• After I/O starts, control returns to user program
  only upon I/O completion.
• Wait instruction idles the CPU until the next
  interrupt
• Wait loop (contention for memory access).
• At most one I/O request is outstanding at a time,
  no simultaneous I/O processing.
• After I/O starts, control returns to user program
  without waiting for I/O completion.
• System call request to the operating system to
  allow user to wait for I/O completion.
• Device-status table contains entry for each I/O
  device indicating its type, address, and state
  request-related information
• Operating system indexes into I/O device table to
  determine device status and to modify table entry
  to reflect the occurrence of the interrupt.

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Two I/O methods (Cont.)
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Device-Status Table
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I/O communication techniques

• 3 techniques are possible for I/O operation
• Programmed I/O
• Does not use interrupts CPU has to wait for
  completion of each I/O operation
• Interrupt-driven I/O
• CPU can execute code during I/O operation it
  gets interrupted when I/O operation is done.
• Direct Memory Access
• A block of data is transferred directly from/to
  memory without going through CPU

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Programmed I/O

• I/O module performs the action, on behalf of the
  processor
• But the I/O module does not interrupt the CPU
  when I/O is done
• Processor is kept busy checking status of I/O
  module
• Byte by Byte

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Interrupt-Driven I/O

• Processor is interrupted when I/O module ready to
  exchange data
• Processor is free to do other work
• No needless waiting
• Consumes a lot of processor time because every
  word read or written passes through the processor
  and requires an interrupt
• Feasible for slow device, such as keyboard
• Interrupt per byte

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Direct Memory Access (DMA)

• CPU issues request to a DMA module (separate
  module or incorporated into I/O module)
• DMA module transfers a block of data directly to
  or from memory (without going through CPU)
• An interrupt is sent when the task is complete
• Only one interrupt per block
• The CPU is only involved at the beginning and end
  of the transfer
• The CPU is free to perform other tasks during
  data transfer
• Good for high-speed device

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Storage Hierarchy
42
Storage Structure

• Main memory registers and main memory are the
  only storage media that the CPU can access
  directly.
• Secondary storage extension of main memory that
  provides large nonvolatile storage capacity.
• Magnetic disks rigid metal or glass platters
  covered with magnetic recording material
• Disk surface is logically divided into tracks,
  which are subdivided into sectors.
• Cylinder the set of tracks that are at one arm
  position
• The disk host controllers determine the logical
  interaction between the device and the computer.

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Moving-Head Disk Mechanism

• Position (random-access) time
• Seek time move the disk arm to the desired
  cylinder
• Rotational latency for the desired sector to
  rotate to the disk head
• Transfer rate the rate at which data flow
  between the drive and the computer

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Storage Hierarchy

• Storage systems are organized in hierarchy
• Speed (Access time)
• Capacity
• Cost
• Volatility
• As goes down the hierarchy
• Decreasing cost per bit
• Increasing capacity
• Increasing access time
• Decreasing frequency of access of the memory by
  the processor
• Becoming non-volatile

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Storage Hierarchy
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The Hit Ratio

• The data stored in faster memory always have a
  copy in slower memory, except temporary data
• Hit ratio fraction of access where data is in
  the faster memory
• T1 access time for fast memory
• T2 access time for slow memory
• T2 gtgt T1
• When hit ratio is close to 1 the average access
  time is close to T1
• But the size of the faster memory is
  significantly smaller than that of the slower
  memory
• Kick out data when the faster memory is full ?
  data replacement

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Hit Ratio and Effective Access Time
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Locality of Reference

• Locality of reference memory reference for both
  instruction and data tend to cluster over a long
  period of time
• Example once a loop is entered, there is
  frequent access to a small set of instructions.
• Hence once a word gets referenced, it is likely
  that nearby words will get referenced often in
  the near future
• We can replace the data whose last access was
  long long ago
• Thus, the hit ratio will be close to 1 even for a
  small faster memory.

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Caching

• Caching copying information into faster storage
  system
• Main memory can be viewed as a cache for
  secondary storage
• Why using cache memory
• Persistent mismatch between CPU and main-memory
  speeds
• Exploit the principle of locality by providing a
  small, fast memory between CPU and main memory --
  the cache memory
• Requires cache management policy, including
  replacement
• Caching introduces another level in storage
  hierarchy. This requires data that is
  simultaneously stored in more than one level to
  be consistent

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Hardware Protection

• Dual-Mode Operation
• I/O Protection
• Memory Protection
• CPU Protection

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Dual-Mode Operation

• Sharing system resources requires OS to ensure
  that an incorrect program cannot cause other
  programs to execute incorrectly.
• Provide hardware support to differentiate between
  at least two modes of operations.
• User mode execution done on behalf of a user
• A process can access only its own memory
• Prevent process from accessing kernel DS or H/W
  registers that may affect other processes or OS
• Monitor mode (also supervisor mode or system
  mode) execution done on behalf of operating
  system
• Access all kernel data structures and hardware

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Dual-Mode Operation (Cont.)

• Mode bit added to computer hardware to indicate
  the current mode monitor/kernel (0) or user
  (1).
• When an interrupt, fault, or system service
  occurs, hardware switches to monitor mode.

Interrupt/fault/system service
MS-DOS No mode bit
monitor
user
set user mode
Privileged instructions can be issued only in
monitor mode.
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Privileged Instruction

• Instruction to change from user mode to monitor
  mode (Any changes to the mode bit)
• Halt instruction
• Turn the interrupt system on and off
• I/O instruction

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Entering Kernel Mode

• Through a system call
• As the result of an interrupt
• As the result of a process trap

User Process
read()
User Mode
System Call Interface
Kernel Mode
File System
I/O
Hardware
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I/O Protection

• All I/O instructions are privileged instructions
• Users cannot issue I/O instructions directly
• Users must do I/O through OS System Call
• Must ensure that a user program could never gain
  control of the computer in monitor mode (ex., a
  user program that, as part of its execution,
  stores a new address in the interrupt vector).

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I/O Protection and System Call

• Given the I/O instructions are privileged, how
  does the user program perform I/O?
• System call the method used by a process to
  request action by the operating system
• Usually takes the form of a trap to a specific
  location in the interrupt vector.
• Control passes through the interrupt vector to a
  service routine in the OS, and the mode bit is
  set to monitor mode.
• The monitor verifies that the parameters are
  correct and legal, executes the request, and
  returns control to the instruction following the
  system call.

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Use of A System Call to Perform I/O
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Memory Protection

• Must provide memory protection at least for the
  interrupt vector and the interrupt service
  routines.
• And protect user programs from one another
• In order to have memory protection, add two
  registers that determine the range of legal
  addresses a program may access
• base register holds the smallest legal physical
  memory address.
• Limit register contains the size of the range
• Memory outside the defined range is protected.
• Advanced memory protection mechanism will be
  discussed in Chapter 9

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A Base And A limit Register Define A Logical
Address Space
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Memory Protection (Cont.)

• When executing in monitor mode, the operating
  system has unrestricted access to both monitor
  and users memory.
• The load instructions for the base and limit
  registers are privileged instructions.

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CPU Protection

• Timer interrupts computer after specified
  period to ensure operating system maintains
  control
• Timer is decremented every clock tick
• When timer reaches the value 0, an interrupt
  occurs and OS gains the control
• Set the timer the amount of time that a program
  is allowed to run
• Timer commonly used to implement time sharing
  (Chap. 6)
• Set the time to interrupt every N milliseconds
  (time slice)
• Time also used to compute the current time
• Load-timer is a privileged instruction

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Network Structure

• Types
• Local Area Networks (LAN)
• Wide Area Networks (WAN)
• Difference
• Geographical distribution
• Speed
• Error rate
• Connection