EECSCS 370

1
EECS/CS 370

• Review for Exam 4 Part II

2
What to Study?

• 10 questions on I/O
• Lecture notes, L30-L34
• Chapter 8
• 5 questions on prior material
• Lectures 28-29
• Project 4
• Be generally familiar with caches and VM

3
Rooms

• All rooms in the EECS building, dont go to
  DOW!!!!!!!!!!!!!!
• Mahlke lecture
• Normal rooms, 1200, 1301, 1303, 1005
• Go to 1200 if confused
• Tyson lecture
• 1500, 1001, 1003, 1005
• Go to 1500 if confused

4
Virtual Memory
2 entry fully assoc TLB, LRU replmt
Memory 4 pages max
Disk Pages
0
page table
Assume 16 bit virtual addrs, 4 bits for page no,
12 bits for page offset
1
2
Page Table
3
D1000
0
References 0000 R 3678 W 6A00 W 0004 R 6FFC
R 1008 R 3134 R
D1001
1
D1002
2
1000
text1
D1003
3
1001
text2
nomap
4
1002
Istatic1
nomap
5
1003
Istatic2
nomap
6
7
nomap
5
Here are the contents of everthing after
execution of all refs is complete
2 entry fully assoc TLB, LRU replmt
Memory 4 pages max
Disk Pages
0
3 -gt M1
page table
Assume 16 bit virtual addrs, 4 bits for page no,
12 bits for page offset
1
Istatic2
1 -gt M2
2
text2
Page Table
3
Uninit data
D1000
0
References 0000 R 3678 W 6A00 W 0004 R 6FFC
R 1008 R 3134 R
M2
1
D1002
2
1000
text1
M1
3
1001
text2
nomap
4
1002
Istatic1
nomap
5
1003
Istatic2
M3
6
7
nomap
6
Virtual Memory

• How many TLB hits occur for the reference address
  stream on the given virtual memory system?
• 0
• 1
• 2
• 3
• 4

Only the reference of 6FFC R is a hit
7
Virtual Memory

• What are the contents of the page table entry for
  page number 3 after the completion of the
  reference stream?
• M0
• M1
• M2
• M3
• D1003

Page 3 starts on d1003, then it is brought into
M2, then put back onto disk in d1003, then
finally brought brought back into memory in M1
8
Virtual Memory

• How many page transfers are made to/from the
  disk?. You should assume the memory is write
  allocate and writeback.
• 2
• 3
• 4
• 5
• 6

- First 2 references are page faults where the
disk contents are brought into memory 2
transfers - 3rd ref is a page fault, but to a
nomap page, hence no disk transfer - 4th and 5th
references are not page fault, hence no disk
transfers - 6th reference is a page fault, a
dirty page is replaced, (page 3) hence 2
transfers - 7th reference is a page fault, a
read-only page is Replaced (page 0), hence 1
transfer - total 5 transfers
9
Bus Contention

• What is the best contention policy for the back
  side bus?
• Daisy-chained
• Centralized
• Decentralized
• Collision detection
• This bus is usually dedicated so none is needed

10
ECC

• In class, the following encoding of 3 parity bits
  was assumed for a 4-bit data to detect and
  correct all 1-bit errors
• p2 odd(d3,d2,d1) p1 odd(d3,d1,d0), p0
  odd(d2,d1,d0)
• To reduce the number of connections, someone
  proposes the following alternative encoding
• p2 odd(d3,d2) p1 odd(d3,d1,d0), p0
  odd(d2,d1,d0)
• Will this work to detect and correct all 1-bit
  errors?
• (a) yes
• (b) no
• (c) cannot be determined

New code cannot tell the difference between a
d1 and d0 error, hence it will not work!!
11
Disk Terminology

• With a magnetic disk, what does seeking refer to?
• Initiating a disk access by the controller
• Locating the proper platter
• Rotating the disk to the proper sector
• Moving the head radially to the right track
• Reading the bytes off the sector

12
Disk Access

• A program repeatedly performs the following 3
  steps 1) read a 4k block of data from disk, 2)
  process the data, and 3) write out a 4k block
  elsewhere on the disk. Each block is contiguous
  and randomly located on a single track on the
  disk. Whats the overall speed of the system in
  blocks processed per second?
• (Note assume the processor and disk are not being
  used for anything else, and there is no overlap
  between processing and disk access)

13
Disk Access contd

• Disk stats
• 5400 RPM, 8ms avg seek time, 20 MB/s transfer
  rate, 2ms controller overhead.
• Processing stats
• 20 million clock cycles to process block, clock
  rate is 400MHz.

• 8.1
• 9.5
• 10.9
• 12.3
• 13.7

See next slide for soln
14
Disk Access contd
Total time read time processing time write
time Processing time num cycles cycle
time Cycle time 1/400MHz 1/(400 x 106)
2.5ns per cycle Processing time 20,000,000
cycles 2.5 ns/cycle .05 sec 50ms Read or
write time rotate seek transfer
overhead Rotate 0.5 rotations x 1min/5400
rotations x 60 s/min x 1000ms/s 5.56ms Transfer
4Kb x 1s/20Mb x 1000ms/s (4 x
1024) bytes x 1s/(20 x 1024 x 1024) bytes x
1000ms/s 0.19ms Seek 8ms (given), Overhead
2ms (given) Read or write time 5.56ms 8ms
0.19ms 2ms 15.75ms Total time 15.75ms
50ms 15.75ms 81.5ms Processing rate 1block
/ 81.5ms x 1000ms/s 12.3 blocks/s
15
Graphics

• Why is the RAM on most video cards dual ported?
• Support more colors
• Support higher resolutions
• Most cost effective
• Reduce refresh time
• Enables the RAM to be used by the CPU for other
  purposes

16
Graphics

• How much video RAM is required to support
  1024x768 resolution with 65000 possible colors
  per pixel?
• 1MB
• 2 MB
• 4 MB
• 8 MB
• 16MB

Table to hold colors 65000 entries,
ceil(log2(65000)) 16 So, 16 bits needed per
pixel to index into the Table. 16 bits x 1
byte/8 bits 2 bytes VRAM resolution x num
bytes per pixel 1024 x 768 x 2
1.5MB, round up to nearest answer!
17
Cache - Project 4

• Given the following cache configuration and
  reference stream for the cache used in project 4

Reference stream Load from 4 Store to 27 Store
to 73 Load from 25 Store to 38 Load from 22 Store
to 11 Store to 133
blockSizeInWords 4 numberOfSets
4 blocksPerSet 2 Write allocate Writeback 16-bit
addresses word addressed
18
Cache Project 4

• In debugging your simulator, you discover there
  is an error when Store to 11 is executed, you
  get the incorrect output message below, what is
  the most likely error? (Assume the output is
  correct up to this point)
• _at__at__at_ transferring word 72-75 from the cache to
  nowhere
• Unnecessary write back of clean block
• Fail to write back a dirty block
• Evict FIFO instead of LRU
• Evict MRU instead of LRU
• Set index calculation error

Should be transferring 72-75 from cache to
memory. Since the right block is selected, you
know LRU is ok. However, since 72-75 is dirty, b
is the right answer
19
Cache Project 4 (harder)

• In debugging your simulator, you discover there
  is an error when Store to 11 is executed, you
  get the incorrect output message below, what is
  the most likely error? (Assume the output is
  correct up to this point)
• _at__at__at_ transferring word 24-27 from the cache to
  memory
• Unnecessary write back of clean block
• Fail to write back a dirty block
• Evict FIFO instead of LRU
• Evict MRU instead of LRU
• Set index calculation error

See next slide for explanation
20
Cache Project 4 (harder)
This question is a tough one. At the store to
11, the block that should be replaced is 72-75
instead of 24-27. The proper set is calculated
so you know the answer is not (e). Similarly,
24-27 is dirty, so the dirty bit is handled
properly, so you know its not (a) or (b). And,
(c) or (d) should make sense since the wrong
block was replaced in the set indicating an LRU
problem. Now, looking individually at the store
11 reference, you cannot tell if the MRU or the
FIFO entry was replaced, because 24-27 is
both the FIFO and the MRU, so you CANNOT narrow
down the error further just looking at store
11. So you must consider the previous
replacement, when 20-23 replaced 4-7. 4-7 is the
first into the set, but not the MRU, 36-39 is the
MRU. So, you can conclude that FIFO is being
incorrectly used rather than LRU and this is the
most likely cause of the error.