EECSCS 370

1
EECS/CS 370

• RISC vs. CISC
• Lecture 14

2
Ways to measure your new computer

• Performance
• my computer is faster than yours!
• Cost
• my computer is cheaper than yours!
• Size
• my mp3 player is smaller than yours!
• my machine has more memory than yours!

3
Ways to measure your new computer

• Power consumption
• my laptop can run for 5 hours on a battery!
• Compatibility
• I have a new playstation 2
• Reliability
• my computer works!

4
Classic Sports Network

• RISC vs. CISC
• Great debates from the 1980s
• Reduced Instruction Set Computers (RISC)
• Simple instructions make fast clocks
• Complex Instruction Set Computers (CISC)
• Complex instructions are more like high level
  languages
• You need fewer instructions to get the job done

5
Proponents claims

• RISC
• Clearly superior, that is why they are covered in
  the text (and almost all other texts on
  architecture)
• Load/Store architectures dominate new
  architectures
• CISC
• Almost all processors used in desktop computers
  are CISC
• Clearly the winner, because you probably use one
  get over it!

6
RISC design philosophy

• See what instructions are actually used
• Why add it if you dont use it?
• See if they can be added to the ISA without
  increasing clock time
• No strange decoding
• No complex control

7
CISC design philosophy

• Design the machine to support the languages
  people actually use
• They like functions, give them an instruction
  that really performs a function call
• Transfers control, save live registers, etc.
• Performs a virtual function call?
• If you are going to go get an instruction, make
  it complicated enough to give the processor
  something to do for a while
• You dont need to go out to memory as often
• Your executable program is generally smaller
• An IA32 binary tends to be about 20 smaller than
  MIPS.

8
Classic example from the 70s

• VAX Architecture 1977-1992
• CISC instruction callg
• Calls a procedure with arguments
• Transfer control (of course)
• Point AP (argument ptr) register to arguments
• Create stack frame (by decrementing SP)
• Saves registers specified to be saved (bitmask)
• Bitmask is stored at target address (identifies
  which registers are used in the callee procedure)
• First instruction of procedure is 1 word later

9
CISC gone wild!

• Intel 80x86
• 16 bit registers (AX, BX, CX, DX), stack
• 0,1,2,3 address operand fields available
• Lots of addressing modes
• Basedisplacement (segments)
• Address base register
• powerful instructions loop
• CX must contain iteration count, conditional
  branch to target if decremented CX is not 0.

10
CISC gone wild!

• Next generation
• Bigger registers (32 bit) EAX, EBX, etc.
• But remember to keep the old ones, because old
  instructions use them
• No opcode space left?
• Use one of the 256 possible opcodes as an escape
  (prefix)
• Meaning, this is not the opcode, the next
  byte(s) are
• And now I have a whole new 256 unused opcodes

11
Giving the customers what they want better 3D
gaming

• Next generation graphics!
• MMX new data type
• MMX new instructions

Red
Green
Blue
?
0 7 8 15 16
23 24 31
PADDUSB opcode 0x0F 0xDC Add
unsigned bytes with saturation
12
MMX add
00
FC
4F
00

00
0F
44
00
0 7 8 15 16
23 24 31
00
00
FF
93
13
Who won?

• 15 rounds, everyone changed the channel.
• It turns out to be a non-issue.
• Intel clearly can get their machines to run fast
  (1 GigaHertz)
• How?
• By making the microarchitecture RISC-like and
  converting CISC to RISC during decode.

14
Proof by example

• Pentium Pro microarchitecture
• 12-14 cycle execution
• Based on ?ops RISC like instructions
• 5 cycle decode to translate CISC to RISC
• Faster clock
• Higher CPI (but not much higher as we will see)

15
Another Example

• Transmeta Crusoe
• Unknown architecture
• You cant buy the chip without the software
• Converts IA32 to something
• Executes that something

16
Most recent example

• Pentium 4 microarchitecture
• 20 cycle execution ( a lot sometimes)
• Based on ?ops RISC like instructions
• unspecified decode time to translate CISC to RISC
• Save it in the microarchitecture as RISC
• Faster clock
• Higher CPI (but not much higher as we will see)
• Way to complex to cover in 370!

17
Current Debate

• Do architectures even matter?
• Why not just have the compiler
• Generate the machine code,
• Creating a new instruction set, and
• Design the microarchitecture while its at it
• Outputting a description ready for the
  fabrication plant!

Silicon compiler
Synthesized Processors