Computer Systems Architecture

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Computer Systems Architecture

• Chapter 3
• Functional units and the fetch-execution cycle

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Outline

• Basic components and their interconnection
• Bus structure
• Executing instruction fetch-execution
• Interrupts and their impact on execution
• Synchronous vs. asynchronous

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Top-level components
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Top Level Components View
Text/code
ALU
data
stack
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Interconnect components

• There are a number of possible ways to
  interconnect components
• Single and multiple BUS structures are most
  common
• e.g. Control/Address/Data bus (PC)
• e.g. PCI

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Illustrate bus connection
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Individual Buses
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Data Bus

• Carries data
• Remember that there is no difference between
  data and instruction at this level
• Width is a key determinant of performance
• 8, 16, 32, 64 bit

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Address bus

• Identify the source or destination of data
• e.g. CPU needs to read an instruction (data) from
  a given location in memory
• Bus width determines maximum memory capacity of
  system
• e.g. 8080 has 16 bit address bus giving 64k
  address space

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Control Bus

• Control and timing information
• Memory read/write signals
• I/0 read/write signals
• Interrupt request/ACK
• Bus request/grant
• Clock signals

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Memory size vs. machine bits
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Single Bus Problems

• Lots of devices on one bus leads to
• Propagation delays
• Long data paths mean that co-ordination of bus
  use can adversely affect performance
• If aggregate data transfer approaches bus
  capacity
• Most systems use multiple buses to overcome these
  problems

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Traditional (ISA)(with cache)
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High Performance Bus
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Bus Types

• Dedicated
• Separate data address lines
• Multiplexed
• Shared lines
• Address valid or data valid control line
• Advantage - fewer lines
• Disadvantages
• More complex control
• Ultimate performance

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Bus Arbitration

• More than one module controlling the bus
• e.g. CPU and DMA controller
• Only one module may control bus at one time
• Arbitration may be centralised or distributed

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Centralised Arbitration

• Single hardware device controlling bus access
• Bus Controller
• Arbiter
• May be part of CPU or separate

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Distributed Arbitration

• Each module may claim the bus
• Control logic on all modules
• A communication pathway connecting two or more
  devices
• Usually broadcast
• Often grouped for different proposes
• A number of channels in one bus
• E.g. 32 bit data bus is 32 separate single bit
  channels
• E.g. Control, address, and data buses

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PCI Express
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PCI Bus
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CPU and Control Unit

• For each operation a unique code is provided
• e.g. ADD, MOVE
• A hardware segment accepts the code and issues
  the control signals

regs
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CPU components

• The Control Unit and the Arithmetic and Logic
  Unit (ALU) constitute the CPU
• Data and instructions need to get into the CPU
  for processing and results out
• Input/output
• Temporary storage of code and results is needed
  by CPU, e.g. registers

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How CPU works- instruction Cycle

• Two steps
• Fetch
• Execute

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Fetch Cycle

• Program Counter (PC) holds address of next
  instruction to fetch
• Processor fetches instruction from memory
  location pointed to by PC
• Increment PC
• Unless told otherwise
• Instruction loaded into Instruction Register (IR)
• Processor interprets instruction and performs
  required actions

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Execute Cycle

• Processor-memory
• data transfer between CPU and main memory
• Processor I/O
• Data transfer between CPU and I/O module
• Data processing
• Some arithmetic or logical operation on data
• Control
• Alteration of sequence of operations
• e.g. jump
• Combination of above

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fetch and execution Mov AX 0x100
1
2
3
4
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Example Add 940 941 -gt941
940-gtAC
Load ac 940
940941-gtAC
Add ac 941
AC-gt941
Store 941 ac
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Instruction Cycle - State Diagram
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Speed-up execution
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Synchronous Timing Diagram
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Example Synchronous timing
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Example Asynchronous timing
ALE
M E M
C P U
DTA