VLSI SIMULATION AND TEST GENERATION

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VLSI SIMULATION AND TEST GENERATION
FACULTY OF ELECTRICAL ENGINEERING
BELGRADE

• Student Marija Stojsavljevic 226/97
• gemini_at_verat.net
• Professoor dr Veljko Milutinovic
• Assitant Gvozden Marinkovic

Belgrade, 20.12.2002
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Introduction

• Simulators
• Test generators
• The advantages of test generator using the
  principles of logic simulator
  
• Using a cost function

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The testing problem

• Fault modeling
• Test generation
• Measures of test quality

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The testing techniques

• DFT techniques
• for purely combinational or synchronous
  sequential circuits
  
• BIST (Built In Self Test)
• Testing with test vectors

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Logic simulation and fault analysis

• Circuit modeling
• - behavior
• - gate
• - switch
• - circuit
• mixed
• Signal modeling
• - analog
• - digital

• Modeling of delays
• - zero delay
• - unit delay
• - multiple delay
• Simulator
• Event-driven simulation

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Event-driven simulation
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Fault modeling

• Stuck faults
• Fault collapsing
• - equivalence fault collapsing
• - dominance fault collapsing
• Other fault models
• - memories
• (1) single cell stuck
• (2) adjacent cell coupling
• (3) pattern-sensitive faults
• - PLA
• (1) cross-point faults
• (2) bridging faults

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Equivalence fault collapsing
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Fault Simulation

• Measures of test quality
• - reject ratio
• - fault coverage
• Methods of fault simulation
• serial
• paralel
• deductive
• concurrent

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Deductive simulation
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Test generation approaches

• exaustive
• random
• algorithmic

• circuits must be synchronous
• limited number of flip-flops
• limited number of gates
• limited number of vectors per fault
• circuit delays must be neglected

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Test generation for combinational circuits

• Path sensitization approach
• D-algorithm
• PODEM
• FAN algorithm
• Subscripted D-algorithm
• CONT algorithm
• Boolean difference approach

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Path sensitization

• justification
• implication
• propagation
• backtracking
• propagation is impossible
• backtrack to a previous step propagation is
  impossible again
  
• backtrack to a previous step
• propagation

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D-algorithm

• forward implication
• D-drive the fault effect is propagated toward
  primary outputs
  
• backward justification (consistency check)

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PODEM

• Value assignment
• defining an objective
• activating the fault effect
• propagating the fault effect toward a primary
  output

START
0
1
unchecked assignment
1
0
backtracking
1
0
backtracking
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Subscripted D-algorithm

• subscripting symbols
• forward-propagating D0 using the normal
• D-algorithm
• Dj , j1..n are propagating backward to primary
  inputs
  
• all the faults related to this gate are
  determined by inspecting the symbols at primary
  inputs
  

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Boolean difference approach
F(x) the function of the fault-free circuit
F(x) the function of the circuit in the
presence of a given fault

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Generisanje testova za sekvencijalna kola

• Iterative array approach
• Extended D-algorithm
• Nine-value algorithm
• Backtrace algorithms
• SCRIPTSS

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Iterative array approach
a 1 b 0 c 0/1
Previous time frame
Current time frame
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Simulation-based directed-search approach

• Principle of directed search
• - involves no backtracking
• - deals with circuit-delays
  in a very natural way
  
• - asynchronous sequential
  circuits can be handled
  
• An overview of the new method
• The unit Hamming distance heuristic
• Cost

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Examples of cost curves
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Threshold-value simulation

• TV model
• determination of thresholds
• fanin-dependent TV model
• TV simulation with three states

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Threshold-value model

• Vi the value of line i

Determination of thresholds
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Fan-in depended threshold-value model
1-TOR(V)
1-TAND(V)
1-V
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The solution
V
V
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Test generation using threshold-value simulation
0
E
A B C
0.0 (0.0)
0

• The cost function

0.0 (0.0)
F
0

• compute the cost for a
• random vector
• compute the cost for all its
• neighbors defined as vectors
• at unit Hamming distance
• the next vector is the neighbor
• that has the lowest cost

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Requirements of sequential test generator

• Cost computation
• Initialization
• Race analysis
• Feedback loop analysis
• Switching the target fault
• Synchronous and asynchronous modes

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Race analysis
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Feedback loop analysis
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Program
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Eksperimentalni rezultati
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Test generation in concurrent fault simulator

• three-phase test generation
• - initialization
• - concurrent fault detection
• - single fault detection
• cost
• - activation fault
• - propagation fault

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Concurrent fault detection
Pocetni vektor
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Example for distance cost function
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Program
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Fault coverage
Fault number
Fault number
800
800
600
600
CONTEST
CONTEST
400
400
TVSET
RANDOM
RANDOM
200
200
0
0
1
10
100
1
10
1000
10,000
100
1000
10,000
Vectors
Vectors
TLC circuit
MULT4 circuit
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Experimental results
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