ECE 425 - VLSI Circuit Design - PowerPoint PPT Presentation

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ECE 425 - VLSI Circuit Design

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Title: ECE 313 - Computer Organization Author: John Nestor Last modified by: John Nestor Created Date: 8/16/2001 7:25:29 PM Document presentation format – PowerPoint PPT presentation

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Title: ECE 425 - VLSI Circuit Design


1
ECE 425 - VLSI Circuit Design
  • Lecture 19 - Architecture Design Analog-Digital
    Conversion
  • Spring 2007

Prof. John NestorECE DepartmentLafayette
CollegeEaston, Pennsylvania 18042nestorj_at_lafayet
te.edu
2
Announcements
  • Reading
  • Book 8.1-8.4, 7.1-7.3

3
Where we are
  • Last Time
  • Design for Test, Built-in Self Test
  • Today
  • System Design Datapath/Controller Design
  • Aside Datapath/Controller Example in VHDL
  • Comparators
  • A/D Conversion
  • Discuss Project

4
The Datapath-Controller Abstraction
  • A higher-level description of chip organization
  • Key idea break up design into two parts
  • Datapath- components that manipulate data
  • Controller - FSM that controls datapath modules

5
Steps in Architecture Design
  • Propose data unit components
  • functions performed
  • data inputs / outputs
  • control inputs - perform operation when asserted
  • status outputs - condition info for control unit
  • Design control-unit FSM
  • Respond to ext. inputs, status values from data
    unit
  • Generate control signals to drive data unit,
    external outputs
  • Control-Unit Representations
  • Traditional "bubble and arrow" state diagram
  • Direct coding in HDL

6
Example Digital Lock
  • Accept 4-bit BCD digits from keypad
  • KRDY - true while button is pressed
  • KIN - 4-bit input
  • Compare digits with four successive "thumbwheel
    switches" for combination setting
  • open lock if all four digits are right
  • otherwise, go back and start over

4
START
SW0
Digital Lock Unit
4
Thumbwheel Switches - Combination
SW1
Keypad
4
SW2
4
4
1
2
3
SW3
4
5
6
KRDY
OPEN
7
8
9
0
7
Digital Lock Architecture
8
Digital Lock Datapath Organization
9
Digital Lock Control
  • Assert START1
  • Wait for KRDY0, then KRDY1
  • Check if KIN D0
  • Wait for KRDY0, then KRDY1
  • Check if KIN D1
  • Wait for KRDY0, then KRDY1
  • Check if KIN D2
  • Wait for KRDY0, then KRDY1
  • Check if KIN D3 and OPEN if it is

10
Digital Lock Control - State Diagram
NOTE Outputs are listed in the following
order S1 S0 START OPEN
11
A Crash Course in VHDL
  • Verilog Construct
  • module interface
  • module body
  • always block
  • _at_(posedge clk)
  • single wires
  • wire vectors
  • VHDL Construct
  • entity
  • architecture
  • process
  • WAIT UNTIL
  • signals of type STD_LOGIC
  • signals of type STD_LOGIC_VECTOR

12
VHDL Example Digital Lock
  • Entity lock_dp Lock datapath
  • Entity lock_fsm Lock controller FSM
  • Entity lock structural assembly of datapath, FSM

13
Lock Datapath - Entity
  • library IEEE
  • use IEEE.std_logic_1164.all
  • use IEEE.std_logic_arith.all
  • entity lock_dp is
  • port( kin, d0, d1, d2, d3 in
    std_logic_vector(3 downto 0)
  • sel in std_logic_vector(1 downto 0)
  • eql out std_logic
  • )
  • end lock_dp

14
Lock Datatpath - Architecture
  • architecture behavior of lock_dp is
  • begin
  • process (kin, d0, d1, d2, d3, sel)
  • begin
  • case (sel) is
  • when "00" gt
  • if (d0 kin) then eql lt '1'
  • else eql lt '0'
  • end if
  • when "01" gt
  • if (d1 kin) then eql lt '1'
  • else eql lt '0'
  • end if
  • when "10" gt
  • if (d2 kin) then eql lt '1'
  • else eql lt '0'
  • end if
  • when "11" gt
  • if (d3 kin) then eql lt '1'

15
Lock FSM Entity
  • library IEEE
  • use IEEE.std_logic_1164.all
  • use IEEE.std_logic_arith.all
  • entity lock_fsm is
  • port( clk, krdy, eql in std_logic
  • sel out std_logic_vector(1 downto 0)
  • openlock, start out std_logic
  • )
  • end lock_fsm

16
Lock FSM Architecture - Part 1
  • architecture behavior of lock_fsm is
  • type state_type is (wait10, wait01, tst0,
    wt10a, wt01a, tst1, wt10b,
  • wt01b, tst2, wt10c,
    wt01c, tst3 )
  • signal cs, ns state_type wait01
  • begin
  • comb process(cs, krdy, eql)
  • begin
  • sel lt "--" -- default
    values
  • openlock lt '0' start lt '0' -- default
    values
  • case (cs) is
  • when wait01 gt
  • start lt '1'
  • if (krdy '1') then ns lt tst0
  • else ns lt wait01
  • end if
  • when tst0 gt
  • sel lt "00"
  • if (eql '1') then ns lt wt10a

17
Lock FSM Architecture - Part 2
  • when wt01a gt
  • if (krdy '1') then ns lt tst1
  • else ns lt wt01a
  • end if
  • when tst1 gt
  • sel lt "01"
  • if (eql lt '1') then ns lt wt10b
  • else ns lt wait10
  • end if
  • when wt10b gt
  • if (krdy '0') then ns lt wt01b
  • else ns lt wt10b
  • end if
  • when wt01b gt
  • if (krdy '1') then ns lt tst2
  • else ns lt wt01b
  • end if
  • when tst2 gt

18
Lock FSM Architecture - Part 3
  • when wt10c gt
  • if (krdy '0') then ns lt wt01c
  • else ns lt wt10c
  • end if
  • when wt01c gt
  • if (krdy '1') then ns lt tst3
  • else ns lt wt01c
  • end if
  • when tst3 gt
  • sel lt "11"
  • if (eql '1') then openlock lt '1'
  • end if
  • ns lt wait10
  • when wait10 gt
  • if (krdy '0') then ns lt wait01
  • else ns lt wait10
  • end if
  • end case
  • end process comb

19
Lock Structure - Part 1
  • for all lock_dp use entity work.lock_dp
    (behavior)
  • for all lock_fsm use entity work.lock_fsm
    (behavior)
  • signal s_eql std_logic
  • signal s_sel std_logic_vector(1 downto 0)
  • begin
  • DP lock_dp port map(kingtkin, d0gtd0, d1gtd1,
    d2gtd2, d3gtd3,
  • selgts_sel, eqlgts_eql)
  • FSM lock_fsm port map(clkgtclk, krdygtkrdy,
    selgts_sel, eqlgts_eql)

20
Lock Structure - Part 2
  • entity lock is
  • port( clk, krdy in std_logic
  • kin, d0, d1, d2, d3 in
    std_logic_vector(3 downto 0)
  • openlock, start out std_logic
  • )
  • end lock
  • architecture structure of lock is
  • component lock_dp is
  • port( kin, d0, d1, d2, d3 in
    std_logic_vector(3 downto 0)
  • sel in std_logic_vector(1 downto 0)
  • eql out std_logic
  • )
  • end component
  • component lock_fsm is
  • port( clk, krdy, eql in std_logic

21
A/D Conversion
  • Basic Circuit Structure

22
A/D Conversion - Naïve Approach
23
A/D Using Successive Approximation
24
A Possible SAR Design
25
SAR FSM State Diagram
26
How do we make a Comparator?
  • One way use a high-gain differential amplifier
  • Example Designs From P. Geiger, P. Allen, and N.
    Strader, VLSI Techniques for Analog and Digital
    CircuitsMcGraw-Hill, 1990
  • Two-stage comparator Fig. 6.6-7, p. 505

27
Alternative Approach Auto-Centering Comparator
  • ø1, ø2 - Non-overlapping two-phase clocks

28
Alternative Approach Zero-Centering Comparator
  • ø1 high - auto-centering

ON
ON
OFF
-VA-VDD/2
Vi1 Vo1 VDD/2
29
Alternative Approach Auto-Centering Comparator
  • ø2 high, ø1 low - evaluation

OFF
OFF
ON
-VA-VDD/2
VE - (VA-VDD/2)
30
Preliminary Layout - Auto-Centering Comparator
31
Additional IssuesAuto-Centering Comparator
  • Isolating comparator output during auto-centering
  • VDD/2 values can propagate and cause problems, so
  • add a flip-flop to isolate output from other
    logic
  • Generating clocks
  • non-overlapping ø1, ø2 and ø1bar, ø2bar
  • generating clock for SAR

32
Clock Generation for the A/D Converter
  • Phases f1, f2 need to be non-overlapping
  • Trigger output flip-flop on falling edge of f2
  • New phase f3 needed to control SAR

D
Q
ø2
33
Verilog Code - Clock Generator (Part I)
  • module cclock3 (mclk,reset,phi1,phi1bar,phi2u,phi2
    ubar,phi3,cmpd,cmpq)
  • input mclk, reset, cmpd
  • output phi1,phi1bar,phi2u,phi2ubar,phi3,cmpq
  • reg 20 Q
  • reg cmpq
  • assign phi1 Q2
  • assign phi1bar phi1
  • assign phi2u Q1
  • assign phi2ubar phi2u
  • assign phi3 Q0

34
Verilog Code - Clock Generator (Part 2)
  • always _at_(negedge mclk) begin
  • if ( reset ) Q lt 3'b100
  • else if ( Q 3'b000
  • ((Q2 Q1) (Q2 Q0) (Q1
    Q2)) )
  • Q lt 3'b100
  • else Q lt Q0,Q21
  • end
  • always _at_(negedge phi2u) cmpq lt cmpd
  • endmodule

35
Synthesized Layout - Clock Generator
36
Overall Layout - Comparator Block
37
More about Comparator cell
  • Using the cell
  • Location of cells /home/nestorj/compare/.mag
  • Top-level cell comparator
  • Connections
  • MCLK- master clock from input pin
  • phi3 - clock for your SAR
  • VI, VE - analog inputs
  • GT - digital output

38
Controlling sv2mag
  • Controlling rows in layout
  • sv2mag -wolfeflags -r n
  • Controlling pin placment
  • create a file module.pins for db file
    module.db
  • Example file cclock3.pins
  • phi1bar top 0.01
  • phi1 top 0.02
  • phi2 top 0.13
  • phi2bar top 0.14
  • cmpd top 0.2
  • cmpq right 0.9
  • phi3 right 0.8
  • mclk bot 0.45
  • reset bot 0.55

39
Project Assignment
  • Build Successive Approximation A/D using
  • DAC from Labs 5-7
  • Comparator discussed here
  • Successive-approximation circuit with added
    features
  • Include scan logic with extra pins TEST, SCAN_IN,
    SCAN_OUT
  • Include hardware to record the maximum converted
    value since the last reset
  • Combine to form one half a MOSIS tiny chip
  • Simulate complete design in PSpice

40
Project Milestones
  • April 17 Code simulate Verilog SAR Design
  • April 24 Floorplan layout for complete
    chip combine SAR, DAC, and Comparator
  • May 1 Simulate complete core integrate into
    chip pad frame
  • May 11 Final Report Due
  • May 28 Successful chips submitted to fab

41
Coming Up
  • Chip Packaging
  • I/O Pads
  • Floorplannning
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