ECE 425 - VLSI Circuit Design

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ECE 425 - VLSI Circuit Design

• Lecture 20 - Chip-Level Design
• Spring 2007

Prof. John NestorECE DepartmentLafayette
CollegeEaston, Pennsylvania 18042nestorj_at_lafayet
te.edu
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Announcements

• Reading
• Book 7.1 - 7.4
• Where We Are
• Last Time
• Sequential Logic Storage Elements
• Sequential Logic Testing
• Today
• Chip-Level Design
• Packaging
• Pad Design
• Floorplanning

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Overview - Chip-Level Design

• Packaging
• Pad Design
• Floorplanning

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Chip Packaging

• Purposes of Packaging
• Protect chip die from damage
• Provide connection points to PC board
• Conduct heat away from chip
• External connection Pins
• Internal connection Pads
• Connections performed by bonding machine

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Common package types

• Dual-inline package (DIP)
• PLCC
• Surface mount
• Pin-grid array
• Ball-grid array
• Flip-chip
• Multi-chip modules

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Some Common Packages
DIP
PGA
PLCC
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DIP Package

• Used in early chips
• Not popular today due to size, pin limits
• MOSIS chips 40-pin DIPs

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Surface-Mount Package

• Mechanically mounted on PC board
• Smaller than DIPs

Graphic Source MemMan.com
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Ball Grid Array Detail
BGA
Graphic Source Analog Devices,
Inc. http//www.analog.com/technology/dsp/EZAnswer
s/manufacturing/bga/background.html
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Chip Lead Inductance

• Recall inductor voltage
• V L(di/dt)
• Result voltage spikes when current changes
  rapidly (like, on a clock edge)
• Example (from Wolf book)
• L 0.5 nH
• iL 1A
• vL 0.5 V.
• Workaround use multiple Vdd, Gnd pins(Wolf
  Book First Pentium had 497 each!)

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I/O Pads

• Pads attach chip to "outside world"
• Wires to pins are bonded to pads on top-level
  metal
• Output pads must drive large loads
• Input pads must protect from ESD (Electrostatic
  Discharge)
• Pad cells - connect to form a pad frame
• Pad locations
• Common approach pad frame around periphery of
  chip
• Less common approach pads across entire chip
  surface
• Some advanced packaging systems bond directly to
  package without bonding wire

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Pad Frame Organization
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Pad Frame Organization

• Must supply power/ground to each pad as well as
  chip core.
• Positions of pads around frame may be determined
  by pinout requirements on package.
• Want to distribute power/ground pins as evenly
  as possible to minimize power distribution
  problems.

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Input Pads

• Problem Electrostatic Discharge (ESD) can
  destroy circuit
• high voltages "punch through" gate oxide
• Irreversible damage to transistors
• Solution "Lightning Arrestor"(See Fig. 7-22, p.
  389)
• series resistor
• clamping circuits

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Input Pads

• Basic Circuit
• Refinements
• NPN-transistors as clamps (see book)
• MOS transistors as clamps (output drivers in
  bidirectional pad?)

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Output Pads

• large transistors used to drive external loads
• note need for buffering to drive pad transistors

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Bidirectional pads

• Combine input, output circuit structures
• Input mode both output transistors OFF
  ("tristate" mode)
• Output mode one output transistor ON

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The MOSIS 1.6µm pad frame

• Developed by Jeff Sondeen, USC ISI
• A set of pads designed to form a ring
• Bidirectional Pads
• Input Pads (Bidirectional Pad with EN0)
• Output Pads (Bidirectional PAD with no output)
• Power Supply Pads
• "Empty" Pads
• Connect by abutment to form complete ring
• Pad Frame - fully assembled pad ring
• More info available at ftp//ftp.isi.edu/pub/son
  deen/

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MOSIS Pad -----
- Frame
SCNA.80.2000
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MOSIS Pad Frame - IO Pad Cell
97 X 134 l
Gnd!
Vdd!
IN
Inb
EN
out
InUnb
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IO Pad Design

• Jeff Sondeens ASCII Art Schematic
• 
  -----
• 
  ---- PAD
• 
  -----
• 
  -
• Vdd
  \
• ---------
  - / 150 ohm
• 
  GND \
• -- -- ENABLE
  
• --0 0---------
  Vdd
• -- --
  
• 
  --
• ----------------------------
  0 P
• 
  --
• ENABLE -- -- ENABLEbar
  
• ------------ 0--------
  ------
• -- --
  IN_unbuffered
• 
  --
• ---------------------------
  - N ---

Sourceftp//ftp.mosis.org/pub/sondeen/magic/SCNA.
80.PADS.2000/README
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Notes about ESD Protection

• 1. Thick-Field Oxide transistor of size W/L
  600/3 microns,
• 2. 150 ohms N_diffusion resistor/diode, and
• 3. Tri-state output drivers as pair of diode
  clamps.
• ESD results have been reported to exceed 2000
  volts (in Orbit 2.0 um fab) but these results
  have not been confirmed by Mosis.

Sourceftp//ftp.mosis.org/pub/sondeen/magic/SCNA.
80.PADS.2000/README
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MOSIS Pad Frame - Vdd Pad Cell
97 X 134 l
Gnd!
Vdd!
Vdd!
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MOSIS Pad Frame - Analog, Power Pads
analog (for VI, VE)
power (for VRplus, VRminus)
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MOSIS Pad Frame - Corner Detail
Gnd!
Vdd!
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A/D Project Pad Frame
Location /home/nestorj/PadFrame/adcframe04.mag
2570l
2570l
1060l
1060l
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ADC Frame Notes

• Two projects per chip die
• Chip split vertically
• Design your layout top level cell to drop into
  padframe on left (or right) side

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Coming Up

• Floorplannning
• Subsystem Design