OFDM Receiver Design

1
OFDM Receiver Design

• Yun Chiu, Dejan Markovic, Haiyun Tang, Ning Zhang
• chiuyun, dejan, tangh, ningzh_at_eecs.berkeley.edu
  
• EE225C Final Project Report, 12 December 2000
• Department of EECS, UC Berkeley

2
Outline

• Overview
• Introduction to OFDM
• 802.11a system specification
• Block Description
• Synchronization
• FFT
• Viterbi
• SVD
• System Integration and Simulation
• Conclusion

3
Introduction to OFDM

• Basic idea
• Using a large number of parallel narrow-band
  sub-carriers instead of a single wide-band
  carrier to transport information
• Advantages
• Very easy and efficient in dealing with
  multi-path
• Robust again narrow-band interference
• Disadvantages
• Sensitive to frequency offset and phase noise
• Peak-to-average problem reduces the power
  efficiency of RF amplifier at the transmitter
• Adopted for various standards
• DSL, 802.11a, DAB, DVB

4
OFDM Signal Representation

• Data set to be encoded on sub-carriers
• IFFT at transmitter
• FFT at receiver

5
Cyclic Prefix
Tg
T
Multi-path components
tmax
Tx
T
Sampling start
6
802.11a System Specification

• Sampling (chip) rate 20MHz
• Chip duration 50ns
• Number of FFT points 64
• FFT symbol period 3.2ms
• Cyclic prefix period 16 chips or 0.8ms
• Typical maximum indoor delay spread lt 400ns
• OFDM frame length 80 chips or 4ms
• FFT symbol length / OFDM frame length 4/5
• Modulation scheme
• QPSK 2bits/sample
• 16QAM 4bits/sample
• 64QAM 6bits/sample
• Coding rate ½ convolutional code with constraint
  length 7

7
OFDM System Block Diagram
8
Synchronization

• Frame detection
• Frequency offset compensation
• Sampling error
• Usually less 100ppm and can be ignored
• 100ppm off 1 of a sample every 100 samples

Tg
T
Frame start
9
Channel Estimation
10
System Pilot Structure
11
Synchronization, Frequency Offset Compensation
12
Outline

• IEEE 802.11a OFDM Transmitter Model
• Receiver Synchronization Module
• A Robust Double Correlation (Correlation
  Auto-Correlation) Based Algorithm
• Receiver Frequency Offset Estimation Module
• A Coarse-Fine Joint Estimation Algorithm with
  Decision-Alignment Error Correction
• Receiver Frequency Offset Compensation Module
• Performance Summary

13
IEEE 802.11a OFDM Txer
14
Short Long Preambles
Short Preamble
Long Preamble
15
Correlation of Short Preamble
Correlation
Fine Timing
Auto-Correlation
Coarse Timing
16
Synchronization
Moving Auto-Corr. Unit
Moving SP Corr. Unit
17
Impairments Multi-Path Channel
18
Impairments Frequency Offset
19
Fine Frequency Offset Est.
Accumulator
Complex Multiplier
Sync. Signal
20
Coarse-Fine Joint Estimation Decision
Alignment Error Correction
Average over 64 chips
Average over 16 chips
100ppm Dfc _at_ 5.8GHz
Coarse
Fine
21
Frequency Offset Compensation
Decision Alignment
Channel
Joint Coarse-Fine Est.
Offest Corr.
22
Performance Summary
23
FFT
24
Pipelined FFT Architecture
Sel
Re
Im
Re
Im
Sel
-1
W
Count
xn
, -j, 1
Xk

Butterfly
Butterfly
Butterfly
2
N/2
N/4
25
Summary of FFT Block
26
System Simulations and Viterbi Decoder
27
System Simulation
28
Problems to be Handled

• Constant over packet frame use long preamble
• Slowly varying frequency selective fading channel
• Symbol boundary offset
• Varying across OFDM symbols use pilot channels
• Phase offset
• Residue frequency offset

29
Frequency Selective Fading Channel

• Time domain channel model
• 8-tap delay line (400ns delay spread)
• amplitude exponential decaying profile
• phase random

30
Channel Compensation

• One-tap equalizer for each sub-carrier
• 1)
• 2)
• Soft-input Viterbi Decoder
• Improve BER with AWGN
• Protect against frequency selective fading

31
Simulation Results

• Simulation parameters
• frequency offset
• (-100ppm to 100ppm)
• frequency selective
• channel
• simulation length
• 104 bits

32
Viterbi Decoder
Z-1
Branch Metric Unit
State Metric Update Unit
Survivor Path Decode Unit

• Block parameters
• Constraint length and code generator
• Survivor path length
• Soft input word length

Parallel architecture with modulo arithmetic
Register-exchange
Number of states 64, Survivor path length 30,
Soft input precision 3-bit
33
Viterbi Decoder Summary
34
SVD Based Channel Estimation
35
Concept of SVD
z'1
Tx
Rx
Channel
?1
Encoding Modulation
Demodulation Decoding
z'4
...
V
V
U
U
?4
BB-equivalent channel models
y H x z
1.
y U ? V x z
SVD
2.
x' V x y' U y z' U z
y' ? x' z'
Unitary X-form
3.
Need to know V at Tx and U,? at Rx
36
SVD Based OFDM System
(A. Klein 00)

• 48 SVD blocks are required!

37
SVD Block for OFDM System
38
Model of Channel Noise
z'1
Tx
Rx
Channel
?1
Encoding Modulation
Demodulation Decoding
z'4
...
V
V
U
U
?4
39
BER Simulation Results

• QPSK modulation
• One narrowband
• carrier
• 4 Rx antennae
• 4 Tx antennae
• Ideal FB from Rx

40
SVD Hardware Realization

• 0.18mm process

90 dense
V(1)
0.47mm
0.47mm
41
Performance Summary (0.25mm)
Building Blocks
inputs
output
P mW
A mm2
D ns
N
1.
5.9
0.156
7.7
C4?1 , C4?1
C1?1
Cmult_Vd_V
8
2.
0.4
0.075
2.1
C1?1 , C1?1
C1?1
Csub_d
8
3.
5.6
0.158
6.9
C1?1 , C4?1
C4?1
Cmult_S_V
8
4.
2.2
0.064
7.2
R1?1 , C4?1
C4?1
Cmult_RS_V
8
5.
1.2
0.027
2.0
C4?1 , C4?1
C4?1
Csum_V_V
8
6.
20.1
0.459
12.3
C4?1 , R1?1
C4?1
Cdiv_V_RS
8
fCLK100MHz
SVD
inputs
output
P mW
A mm2
D ns
N
64
1.74
8.2
R1?1 ,C4?1 , C4?1
C4?1
V_est
8
R1?1 , C4?1
U?_est
8
R4?4 , C4?1
8.2
210
5.54
42
Hardware Realization, Conclusion
43
Overall System Summary
fCLK 20MHz
44
Overall Hardware Breakdown
SVD

• 0.25mm process

Die photo (W. R. Davis et al., CICC01)
45
Porting to a New Technology
Area reduction 58.5
Prof. Wile E. Coyote
46
Entire Design in 0.18mm
Prof. Pink Panter
47
Conclusion and Future Work

• Major building blocks of an OFDM Rx
• Synchronization
• FFT
• Viterbi decoder
• SVD
• OFDM System Simulation
• SVD-based array processing
• Future Work
• Integration of array processing in OFDM
• Interpolation across sub-carriers
• Complete fix point model