ELEC 59700016970001Fall 2005 Special Topics in Electrical Engineering LowPower Design of Electronic

1
ELEC 5970-001/6970-001(Fall 2005)Special Topics
in Electrical EngineeringLow-Power Design of
Electronic CircuitsDynamic Power Glitch
Elimination

• Vishwani D. Agrawal
• James J. Danaher Professor
• Department of Electrical and Computer Engineering
• Auburn University
• http//www.eng.auburn.edu/vagrawal
• vagrawal_at_eng.auburn.edu

2
Components of Power

• Dynamic
• Signal transitions
• Logic activity
• Glitches
• Short-circuit
• Static
• Leakage

3
Power of a Transition
isc
VDD
Dynamic Power CLVDD2/2 Psc
R
Vo
Vi
CL
R
Ground
4
Dynamic Power

• Each transition of a gate consumes CV2/2.
• Methods of power saving
• Minimize load capacitances
• Transistor sizing
• Library-based gate selection
• Reduce transitions
• Logic design
• Glitch reduction

5
Glitch Power Reduction

• Design a digital circuit for minimum transient
  energy consumption by eliminating hazards

6
Theorem 1

• For correct operation with minimum energy
  consumption, a Boolean gate must produce no more
  than one event per transition.

Output logic state changes One transition is
necessary
Output logic state unchanged No transition is
necessary
7
Event Propagation
Single lumped inertial delay modeled for each
gate PI transitions assumed to occur without time
skew
Path P1
1 3
1
0
2 4 6
P2
1
2
3
0
Path P3
5
2
0
8
Inertial Delay of a Gate
Vin
dHLdLH d ---- 2
dHL
dLH
Vout
time
9
Theorem 2

• Given that events occur at the input of a gate
  with inertial delay d at times,
• t1 . . . tn , the number of events at the
  gate output cannot exceed

tn t1 -------- d
min ( n , 1 )
tn - t1

time
t1 t2 t3 tn
10
Minimum Transient Design

• Minimum transient energy condition for a Boolean
  gate

ti - tj lt d
Where ti and tj are arrival times of
input events and d is the inertial delay of
gate


11
Balanced Delay Method

• All input events arrive simultaneously
• Overall circuit delay not increased
• Delay buffers may have to be inserted

4?
1
1
1
1
1
3
1
1
1
1
1
12
Hazard Filter Method

• Gate delay is made greater than maximum input
  path delay difference
• No delay buffers needed (least transient energy)
• Overall circuit delay may increase

1
3
1
1
1
3
1
1
1
1
13
Linear Program

• Variables gate and buffer delays
• Objective minimize number of buffers
• Subject to overall circuit delay
• Subject to minimum transient condition for
  multi-input gate

14
Variables for Full Adder add1b
0
1
0
0
1
1
0
0
1
0
1
1
0
0
1
0
0
1
0
1
0
0
15
Variables for Full Adder add1b

• Gate delay variables d4 . . . d12
• Buffer delay variables d15 . . . d29

16
Objective Function

• Ideal minimize the number of non-zero delay
  buffers
• Actual sum of buffer delays

17
Specify Critical Path Delay
0
1
0
0
1
1
0
0
1
0
1
1
0
0
1
0
0
1
0
1
0
0
Sum of delays on critical path maxdel
18
Multi-Input Gate Condition
d1
0
d
1
1
d
0
0
1
0
1
0
0
d2
d
d1 - d2 d d2 - d1 d
d1 - d2 d
19
Results 1-Bit Adder
20
AMPL Solution maxdel 6
1
2
1
1
1
1
1
2
1
2
2
21
AMPL Solution maxdel 7
3
1
1
1
1
1
2
2
1
2
22
AMPL Solution maxdel 11
5
1
1
1
1
3
2
3
4
23
Original 1-Bit Adder
Color codes for number of transitions
24
Optimized 1-Bit Adder
Color codes for number of transitions
25
Results 1-Bit Adder

• Simulated over all possible vector transitions
• Average power optimized/unit delay
• 244 / 308 0.792
• Peak power optimized/unit delay
• 6 / 10 0.60

Power Savings Peak 40 Average
21
26
References

• E. Jacobs and M. Berkelaar, Using Gate Sizing to
  Reduce Glitch Power, Proc. ProRISC/IEEE Workshop
  on Circuits, Systems and Signal Processing, Nov.
  1996, pp. 183-188 also Int. Workshop on Logic
  Synthesis, May 1997.
• V. D. Agrawal, Low-Power Design by Hazard
  Filtering, Proc. 10th Int. Conf. VLSI Design,
  Jan. 1997, pp. 193-197.
• V. D. Agrawal, M. L. Bushnell, G. Parthasarathy,
  and R. Ramadoss, Digital Circuit Design for
  Minimum Transient Energy and a Linear Programming
  Method, Proc. 12th Int. Conf. VLSI Design, Jan.
  1999, pp. 434-439.
• Last two papers are available at website
  http//www.eng.auburn.edu/vagrawal

27
A Limitation

• Constraints are written by path enumeration.
• Since number of paths in a circuit can be
  exponential in circuit size, the formulation is
  infeasible for large circuits.
• Example c880 has 6.96M constraints.

28
Timing Window

• Define two timing window variables per gate
  output
• ti Earliest time of signal transition at gate i.
• Ti Latest time of signal transition at gate i.

t1, T1
ti, Ti
. . .
i
tn, Tn
Ref T. Raja, Masters Thesis, Rutgers Univ., 2002
29
Linear Program

• Gate variables d4 . . . d12
• Buffer Variables d15 . . . d29
• Corresponding window variables t4 . . . t29 and
  T4 . . . T29.

30
Multiple-Input Gate Constraints

• For Gate 7
• T7 gt T5 d7 t7 lt t5 d7 d7 gt T7 - t7
• T7 gt T6 d7 t7 lt t6 d7

31
Single-Input Gate Constraints
Buffer 19

• T16 d19 T19
• t16 d19 t19

32
Overall Delay Constraints

• T11 lt maxdelay
• T12 lt maxdelay

33
Comparison of Constraints
Number of constraints
Number of gates in circuit
34
Estimation of Power

• Circuit is simulated by an event-driven simulator
  for both optimized and un-optimized gate delays.
• All transitions at a gate are counted as
  Eventsgate.
• Power consumed ? Eventsgate x of fanouts.
• Ref Effects of delay model on peak power
  estimation of VLSI circuits, Hsiao, et al.
  (ICCAD97).

35
Results 4-Bit ALU
Power Savings Peak 33 , Average 21
36
Power Calculation in Spice
V
VDD
Open at t 0
Energy, E(t)
Circuit
Large C
t
Ground
1
1
E(t) -- C VDD 2 - -- C V 2 C VDD (
VDD - V )
2
2
Ref. M. Shoji, CMOS Digital Circuit Technology,
Prentice Hall, 1988, p. 172.
37
Power Dissipation of ALU4
1 micron CMOS, 57 gates, 14 PI, 8 PO 100 random
vectors simulated in Spice
7
6
5
Original ALU delay 3.5ns
4
Energy in nanojoules
3
Minimum energy ALU delay 10ns
2
1
0
0.0
0.5
1.5
2.0
1.0
microseconds
38
F0 Output of ALU4
Original ALU, delay 7 units (3.5ns)
5
0
Signal Amplitude, Volts
Minimum energy ALU, delay 21 units (10ns)
5
0
0
40
120
160
80
nanoseconds
39
Benchmark Circuits
Maxdel. (gates) 17 34 24 48 47 94 43 86
Circuit C432 C880 C6288 c7552
No. of Buffers 95 66 62 34 294 120 366 111
Normalized Power
Average 0.72 0.62 0.68 0.68 0.40 0.36 0.38 0.3
6
Peak 0.67 0.60 0.54 0.52 0.36 0.34 0.34 0.32
40
Physical Design
Gate l/w
Gate l/w
Gate l/w
Gate l/w
Gate delay modeled as a linear function of gate
size, total load capacitance, and fanout gate
sizes (Berkelaar and Jacobs, 1996). Layout
circuit with some nominal gate sizes. Enter
extracted routing delays in LP as constants and
solve for gate delays. Change gate sizes as
determined from a linear system of
equations. Iterate if routing delays change.
41
Power Dissipation of ALU4
42
References

• R. Fourer, D. M. Gay and B. W. Kernighan, AMPL A
  Modeling Language for Mathematical Programming,
  South San Francisco The Scientific Press, 1993.
• M. Berkelaar and E. Jacobs, Using Gate Sizing to
  Reduce Glitch Power, Proc. ProRISC Workshop,
  Mierlo, The Netherlands, Nov. 1996, pp. 183-188.
• V. D. Agrawal, Low Power Design by Hazard
  Filtering, Proc. 10th Intl Conf. VLSI Design,
  Jan. 1997, pp. 193-197.
• V. D. Agrawal, M. L. Bushnell, G. Parthasarathy
  and R. Ramadoss, Digital Circuit Design for
  Minimum Transient Energy and Linear Programming
  Method, Proc. 12th Intl Conf. VLSI Design, Jan.
  1999, pp. 434-439.
• M. Hsiao, E. M. Rudnick and J. H. Patel, Effects
  of Delay Model in Peak Power Estimation of VLSI
  Circuits, Proc. ICCAD, Nov. 1997, pp. 45-51.
• T. Raja, A Reduced Constraint Set Linear Program
  for Low Power Design of Digital Circuits,
  Masters Thesis, Rutgers Univ., New Jersey, 2002.

43
Conclusion

• Glitch-free design through LP constraint-set is
  linear in the size of the circuit.
• LP solution
• Eliminates glitches at all gate outputs,
• Holds I/O delay within specification, and
• Combines path-balancing and hazard-filtering to
  minimize the number of delay buffers.
• Linear constraint set LP produces results exactly
  identical to the LP requiring exponential
  constraint-set.
• Results show peak power savings up to 68 and
  average power savings up to 64.