Prsentation PowerPoint

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Front-end electronic for the ECAL physic prototype
Christophe De La Taille, Julien Fleury, Gisèle
Martin-Chassard
LAL, Orsay, 21st January, 2003
Presented by Julien Fleury
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Plan
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Analogue electronic
Noise of the preamplifier whats new New test
chip sent to founder presentation New test
board for front-end chip
Design of the input PMOS

• Is the gate resistance low ?
• Is the bulk resistance low ?

Optimizing the input transistor allows to reduce
the series noise
Design of the input current source
The first version input current source is made of
NMOS. The shapes of the ENC curves let us think
that the 1/f noise is bigger than expected. Using
a bipolar input current source permits to reduce
the 1/f noise
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Analogue electronic
Noise of the preamplifier whats new New test
chip sent to founder presentation New test
board for front-end chip
ENC
Series noise contribution
Parallel noise contribution
Tp
1/f noise contribution
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Analogue electronic
Noise of the preamplifier whats new New test
chip sent to founder presentation New test
board for front-end chip

• Status
• Submitted November 2002
• Back from founder end of Feb.2003
• Testboard currently in fab

• 4 test cells
• A charge preamplifier
• with bipolar input current source
• A calibration switch
• That integrates the Voltage to Current conversion
• A current feedback operational amplifier
• To be implemented in a multi-gain shaper
• A new track and hold
• With lower pedestal dispersion

Meccano_nov_02
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Analogue electronic
Noise of the preamplifier whats new New test
chip sent to founder presentation New test
board for front-end chip

• Test board designed for
• Extract every useful parameters
• To fix electronic problems
• Study the chip under test beam
• To figure out its behaviour

• Status
• Sent in fab 20th Feb.
• Number of pieces 4

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Interface
Mechanical dimension reminder Connectors and
cables Input/Output
Next version
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Interface
Mechanical dimension reminder Connectors and
cables Input/Output
Slab n1
Thickness 7mm ________________ PCB ?
2.4mm Components ? 4.6mm
Slab n
Slab n-1
There is only small passive component on bottom
layer to save thickness ? Thickness of bottom
components 1mm
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Interface
Mechanical dimension reminder Connectors and
cables Input/Output
First PCB connector
Proposal for next version

• Board to Board connector
• Samtec LSH LHT series

• Board to cable connector
• JST SHL series

• 0.5mm pitch, 2 rows density is
• 4 times bigger than JST connector

• 1mm pitch ? impossible to have
• 40 connexions in 3 cm

• Cables are hard to build
• each pin has to be soldered

• Use of Kapton cables
• easy to solder, custom design to have
• different connector on each end

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Interface
Mechanical dimension reminder Connectors and
cables Input/Output
First PCB connector
Proposal for next version
Calibration
Calibration

• 6 LVDS calibration timing (1 per cal. channel)
• 6 calibration currents

• 12 LVDS calibration timing (1 per cal. channel)
• 1 calibration voltage

Read out
Read out

• LVDS Shift register clock
• LVDS Hold signal (/track)
• LVDS Shift register input
• LVDS shift register reset
• 6 analog output (1 per channel)

• LVDS Shift register clock
• LVDS Hold signal (/track)
• LVDS Shift register input
• LVDS shift register reset
• 2 LVDS shift register output
• 12 differential analog output (1 per channel)

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Interface
Mechanical dimension reminder Connectors and
cables Input/Output
Channel multiplexing

• D latch active on level
• SROUT is useful for serialization of several chip

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Conclusion
Schedule of the next few months
Very Front End and PC Board
Test Meccano_Nov_02
Design CALIB_FLC
Design PCB_FLC V2
Charact. Input PMOS
Test FLC_PHY_1
Noise and uniformity meas. on FLC_PHY1 PCB
For the characterization of the whole FLC_PHY1
PCB functionality ?need of a test read out
system soon