Xilinx Embedded Development Kit

1
Xilinx Embedded Development Kit

• Xilinx Platform Studio (XPS)
• CPE 329
• Winter 2004

2
Normal VHDL Flow

• Design module
• Implement in VHDL
• Synthesize
• Download

3
XPS Flow

• Design system
• Define hardware for system
• Setup software environment
• Write software to implement system
• Synthesize and compile system
• Download implementation

4
Introduction

• Define hardware
• Specifically, create MHS file
• MHS MicroBlaze Hardware Specification
• Add modules to system
• Define memory map
• Connect modules to buses
• Connect non-bus module I/O
• Set any necessary module parameters
• Define user constraints (pin-outs)

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Introduction

• Setup Software Environment
• Create MSS file
• MSS MicroBlaze Software Specification
• Select interface level to devices
• Generate libraries and device drivers to use
• Write software
• C code that implements system
• Use libraries and drivers generated previously
• Add source files to system

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Introduction

• Synthesize and Compile
• Generate netlists to synthesize
• Generate bitstream for download
• Compile system code and libraries
• Update bitstream with compiled code
• Download
• Download bitstream

7
Define Hardware

• Add/Edit Cores Dialog Boxes

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Add Modules to System

• Always add (for this course)
• MicroBlaze module (microblaze)
• BRAM module (bram_module)
• 2 LMB BRAM controllers (lmb_bram_if_cntlr)
• Data side and instruction side
• Add other peripherals as necessary
• GPIO (opb_gpio)
• Timer (opb_timer)
• Change instance names if desired

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Define Memory Map (1)

• None for microblaze and bram_block modules
• Set address range for lmb_bram_if_cntlrs
• Identical address ranges!
• MicroBlaze is Harvard
• GNU compiler is Von Neumann
• Base address is 0x00000000
• High address is 0x00001FFF or lower

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Define Memory Map (2)

• Other modules have minimum memory requirements,
  set these appropriately
• No address ranges may overlap
• LMB memory controllers are only exceptions
• Put modules on each bus on a separate memory
  segment
• LMB modules (memory) assigned in0x00000000-0x0000
  1FFF
• OPB modules assigned in0x00002000-0xFFFFFFFF

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Connect Modules to Buses (1)

• Add buses to system
• OPB opb_v20_v1_10_b
• Data LMB lmb_v10_00_a
• Instruction LMB lmb_v10_00_a
• Rename buses if desired

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Connect Modules to Buses (2)

• Connect buses
• Check box to create a connection
• S slave on bus
• M master on bus
• MS master and slave on bus
• Do not connect instruction OPB (cpu iopb)
• Connect BRAM to controllers
• Select one port for each memory controller
• Rename connector if desired

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Connect Module I/O (1)

• Add all I/O pins to connect
• I/O depends on module
• See documentation or lab assistant for necessary
  I/O to use
• To connect multiple signals
• Select first signal
• Hold Ctrl and select other signals
• Click Connect button
• Net Names that are the same are connected
• External is visible outside system (to pins)

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Connect Module I/O (2)

• Add an external port for signals that are not
  part of a module I/O
• Click Add Port button
• Give signal name (i.e., sclk)
• Give polarity based on signal use
• OUT is output of system
• IN is input to system
• Ignore Port Class (leave NONE)
• Connect to existing net (i.e., sys_clk)

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Set Module Parameters

• Select module from drop down list
• Values listed on right are default
• To change a value
• Select module and parameter
• Click the ltltAdd button
• Change parameter in left window
• See documentation for parameter info
• Click on Open PDF Doc with module selected

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Define User Constraints

• Save in file with ucf extension (e.g.,
  system.ucf) within data folder of main project
  folder
• Text file with one constraint (pin definition)
  per line
• Format for one signal NET net_name LOC
  pinExample NET sys_clk LOC
  B8
• Format for a signal within a vector NET
  net_nameltnumgt LOC pinExample NET
  led_pinlt0gt LOC C15
• pin is found from documentation or lab assistant

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Setup Software Environment
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Device Driver Interface

• Each module may have multiple interfaces
• 0 is a very low level (register-level) interface
• 1 is a higher level (system call-level) interface
• Open S/W Settings for each module
• Right click on module name
• Set Interface Level to desired value
• Set Interface Level of MicroBlaze to 1

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Generate Libraries and Drivers

• Click on toolbar button gtor select from Tools
  menu
• Check for errors
• Most warnings can be ignored

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Write Software
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Write Software

• Implement system functionality in C code
• Use the libraries and drivers generated
  previously when applicable
• Driver API depends on interface level
• Check documentation and generated files for
  information and and API description
• Save source files in a directory you create
• Example my_code in main project directory
• Do NOT store source files in code directory
  within MicroBlaze directory

22
Add Source Files to Project

• Click Add Program Sources button
• Select source file to add
• Click Open
• You may wish to compile code to make sure it is
  syntactically correctCompile gtor run from
  Tools menu

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Synthesize and Compile System
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Synthesize

• Generate net list for system
• XPS generates VHDL for system
• Modules generated based on system definition
• Generate bitstream for download
• Synthesizes VHDL and libraries
• Creates format to use in iMPACT

25
Compile

• Compile code, if not done previously
• Update bitstream
• BRAMs initially empty
• Updating places compiled code in correct memory
  locations of BRAM

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Code Size

• If compilation is successful the size of your
  compiled code is shown
• The code size must be small enough to fit in the
  BRAM block
• If the HEX entry (code size in hexadecimal) is
  larger than the HIGHADDR of the memory
  controllers, then your code will not fit
• Restructure code to decrease size
• Ask lab assistants for hints if needed

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Download
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Download Design (1)

• Use iMPACT tool
• Same as when using ISE
• Only operation not performed in XPS
• Connect JTAG and power to board
• Open iMPACT
• Select Configure Devices gt Click Next
• Select Boundary-Scan Mode gt Click Next
• Select Automatically connect gt Click Next
• A single device should appear

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Download Design (2)

• Assign program file
• implementation/download.bit file
• NOT system.bit (before updating bitstream)
• Ignore the warning about wrong identification
• Right-click device and select Program
• Make sure Verify is UNchecked
• When done your system should be running!

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Summary

• Define hardware for system
• Setup software environment for program
• Write software to implement functionality
• Synthesize and compile system
• Download implementation
• Repeat the steps if the system is changed