Foundations for Datapath Design

1
Foundations for Datapath Design

• Chapter 5
• B. Ramamurthy

2
Background material (Review)

• See Appendices in the CD Esp. Appendix B for
  basics on basic combinational circuit design
• Appendix B also has an introduction to Verilog
• Lets review some Verilog material from Appendix
  B
• A wire specifies a combinational signal. A reg
  (register) holds a value, which can vary with
  time.
• reg 310 X or wire 310
• Values can be 0, 1, z, x
• 4b0100 specifies a 4-bit binary constant with
  the value 4, as does 4d4.

3
More on Verilog

• initial constructs, which can initialize reg
  variables
• continuous assignments, which define only
  combinational logic
• always constructs, which can define either
  sequential or combinational logic
• instances of other modules, which are used to
  implement the module being defined
• Example on always
• always _at_(list of signals that cause reevaluation)
  
• begin
• Verilog statements including assignments and
  other control statements
• end

4
Example for always

• module Mult4to1 (In1,In2,In3,In4,Sel,Out)
• input 310 In1, In2, In3, In4 /four 32-bit
  inputs
• input 10 Sel //selector signal
• output reg 310 Out// 32-bit output
• always _at_(In1, In2, In3, In4, Sel)
• case (Sel) //a 4-gt1 multiplexor
• 0 Out lt In1
• 1 Out lt In2
• 2 Out lt In3
• default Out lt In4
• endcase
• endmodule

5
MIPS ALU

• module MIPSALU (ALUctl, A, B, ALUOut, Zero)
• input 30 ALUctl
• input 310 A,B
• output reg 310 ALUOut
• output Zero
• assign Zero (ALUOut0) //Zero is true if
  ALUOut is 0 goes anywhere
• always _at_(ALUctl, A, B) //reevaluate if these
  change
• case (ALUctl)
• 0 ALUOut lt A B
• 1 ALUOut lt A B
• 2 ALUOut lt A B
• 6 ALUOut lt A - B
• 7 ALUOut lt A lt B ? 10
• 12 ALUOut lt (A B) // result is nor
• default ALUOut lt 0 //default to 0, should not
  happen
• endcase
• endmodule

6
More on controlling the ALU

• 1. Place all combinational logic in a continuous
  assignment or an always block.
• 2. Make sure that all the signals used as inputs
  appear in the sensitivity list of an always
  block.
• 3. Ensure that every path through an always block
  assigns a value to the exact same set of bits.
• The last of these is the easiest to overlook

7
Designing the Main Control Unit

• Entry point for the design is Instruction set,
  types and format
• Three instruction formats R-type, Branch, and
  load/store
• The operation code, opcode field, is in 3126
  bits op50
• The two registers to be read is specified by rs
  and rt 2521, 2016
• Base register for load and store instruction is
  in rs, 2521
• 16-bit offset for the branch equal, load, and
  store is always in position 150
• The destination register is in one of the two
  places for load it is in bit positions 2016
  (rt), for R-type instructions it is in 1511
  rd.
• Thus we need a to add a multiplexer to select
  which field of the instruction is used to
  indicate the register number to be written.

8
Instruction formats
9
Control Unit for the major ALU (Fig. 5.12)
10
Data Path Design DiagramS

• Observe the incremental development in Figures
  5.15 - 5.24