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ATM Switching

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8/21/09. 1. ATM Switching. Presented by. Jes s R os. May 2-3, 2002. ELEE 6399. 2. 8/21/09 ... An ATM switch of size N can be regarded as a box with N input ... – PowerPoint PPT presentation

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Title: ATM Switching


1
ATM Switching
  • Presented by
  • Jesús Ríos
  • May 2-3, 2002
  • ELEE 6399

2
Presentation Outline
  • Definition
  • Characteristics
  • Generic Block Diagram
  • Classification
  • Space Division
  • Time Division
  • Definition - Blocking
  • Definition Buffering
  • Approaches
  • Pros Cons
  • Sharing
  • Space Division
  • Crossbar
  • Banyan Network
  • Others
  • Time Division
  • Shared Memory
  • Shared Medium

3
ATM Switch
  • Definition
  • An ATM switch of size N can be regarded as a box
    with N input ports and N output ports, that
    routes cells arriving at its input ports to their
    desired output ports (destinations)
  • The means by which to allocate the limited
    transmission facilities to users so as to provide
    a certain degree of connectivity among them.

4
ATM Switch Characteristics
  • High-speed interfaces (50 Mbps to 2.4 Gbps)
  • Transports various types of traffic, each with
    different requirements
  • cell loss
  • errors
  • delay an delay jitter (variance in delay)
  • Relays cells (routes and buffers cells) from
    input ports to output ports
  • Provides control and management functions
  • Supports a set of traffic control requirements

5
Generic ATM Switch
6
Generic Switch Architecture
Functional Block Model
7
Switch Classification
  • Space Division Fabrics
  • Time Division Fabrics
  • Combination of the two

8
Switch Classification
  • Space-Division Fabrics
  • All cells flow through the switch at the same
    time, but do so on different paths
  • Multiple concurrent paths are established between
    input and output ports
  • Many cells cross the switching fabric
    simultaneously
  • Constructed from basic switching blocks called
    switching elements (SE) interconnected in a
    specific topology by links
  • Examples are crossbar switch, banyan switch,
    batcher-banyan switch, and many more

9
Space Division Switch
10
Switch Classification
  • Time-Division Fabrics
  • All cells flow through a single resource shared
    by all input and output ports, but do so at
    different times
  • Resource may be either a shared-memory or a
    shared medium such as a bus
  • Most common types are shared-memory switch and
    shared-medium switch

11
Time-Division Switch
OUTPUT 1
INPUT 1
AF
S/P
FIFO
OUTPUT 2
INPUT 2
S/P
AF
P/S
FIFO
TIME DIVISION BUS
...
...
...
...
...
...
INPUT N
OUTPUT N
AF
S/P
FIFO
12
Definition - Blocking
  • Internal Blocking
  • When two or more cells addressed to different
    outputs compete for the same internal link
  • Output Blocking
  • When two or more cells addressed to the same
    external output port arrive within the same cell
    time slot
  • Both result in cell loss due to cell conflict in
    delivery

13
Definition - Buffering
  • Buffers - Storage locations utilized to store
    cells on a temporary basis to prevent cell loss
    whenever port contention occurs
  • Classified based on the location of buffers
  • Input Buffering, Internal Buffering
  • Output Buffering, Re-circulating Buffering
  • Classified based on the memory sharing policy
  • Dedicated buffers
  • Shared buffers
  • Used to prevent blocking

14
Buffering Approaches
15
Buffering Pros Cons
  • Input buffering
  • Head of line blocking
  • Change FIFO buffer to FIRO (First-in-random-out)

16
Buffering Pros Cons
  • Output buffering
  • Optimal in terms of throughput and delay
  • Can add multiple buffers per output to enhance
    delivery of multiple cells per cycle
  • Internal buffering
  • Can create internal head of line buffers
  • Introduces varying delay in cell delivery
  • Recirculating buffers
  • Allows cells to re-enter the internal space
    division network
  • Issues larger network for recirculation
    control mechanism to maintain cell sequence

17
Buffer Sharing
  • Lowers the total amount of buffer space
    requirement
  • Uses statistical sharing
  • Useful in handling traffic bursts
  • If Im getting blown out of the water by a large
    file transfer or video file, I can borrow someone
    elses buffer space to handle the burst
  • Prevents cell loss

18
Multicasting / Broadcasting
  • Broadcast an input to a selected number of
    outputs or to all outputs
  • Video is one such application
  • Shared medium and fully interconnected output
    buffered fabrics
  • Already broadcast ready, so design address
    filters to filter by multicast address as well as
    port address
  • Shared memory fabric
  • Requires additional hardware
  • Can either make multiple copies of cell 2 B
    multicast or can read memory repeatedly
  • Former requires more memory latter requires
    control circuitry

19
Space Division Crossbar Switch
NxN Square Space Switch w/N2 Crosspoints
20
Advantages/Disadvantages
  • Need n(n-1)/2 crosspoints
  • For n 1000, need 500,000 crosspoints
  • Splitting crossbar switch into smaller pieces
  • Connect smaller pieces together to form
    multistage switches as shown on next slide
  • Reduces the number of crosspoints
  • Generates a space division switch

21
Space Division - Banyan
4x4 8x8 Banyan Networks
22
Advantages/Disadvantages
  • Switching performed by simple elements
  • Cells routed in parallel
  • Modular, can scale recursively
  • Implement in hardware
  • Internal blocking (Sorter network)
  • Input buffer
  • Internal buffer
  • Requires routing function
  • Self routing
  • Depending on input, it can route or block (153)

23
Other MINs
  • Batcher-Banyan
  • Benes Network
  • Clos Network
  • Cascaded Banyan
  • Omega Network
  • Delta Network
  • Goals of these networks
  • Minimize cross points to scale the network

24
Time Division - Shared Memory
25
Advantages
  • Output buffers are shared between all ports
  • 100 throughput under heavy load
  • Minimizes the number of buffers for a particular
    cell loss ratio
  • Scalability price
  • Input S/P? Reduce internal speed and to write to
    memory
  • Non-blocking? Multi-stage?

26
Disadvantages
  • Shared memory must operate N times faster
  • Memory access time limited
  • Need fast controller to process header info as
    fast as shared memory rate
  • Issues w/Multi- and Broadcasting

27
Multicast Support 4 Shared-Memory
  • Multiple-write, multiple-read (MWMR)
  • Advantages
  • Cells treated as unicast cells after replication
  • Fair scheme multicast likely to be dropped 1st
  • Disadvantages
  • Cell loss due to worst case scenario
  • Requires reading N2 cells
  • N2 cells to write limited memory cycle time

28
Multicast Support 4 Shared-Memory
  • Single-write, multiple-read (SWMR)
  • Cell stored directly in a separate queue
  • Multiple reads operations performed to output
  • Advantages
  • Prevents writing N2 cells to memory each cycle
  • No additional hardware switch size and fanout
    (N) small
  • Disadvantages
  • Replication process speeds up by factor of N
  • Memory bandwidth limitation if memory size grows
    too big

29
Multicast Support 4 Shared-Memory
  • Single-write, single-read (SWSR)
  • No replication at input
  • Single read for output
  • Replicated at output
  • Dedicated multicast queue and output port (FIFO)
  • Implement w/ Output buffers or Output masks
  • Advantages
  • Efficient (memory space)
  • Efficient (memory access time)
  • Disadvantages
  • Additional hardware for replication (fanout bus)
  • Additional buffer space

30
Multistage Shared Memory Switch Designs
  • Single stage common memory switch provides the
    lowest delay and the highest link utilization
  • Size of single-stage switch limited by
  • Input/output pin limitations
  • Power dissipation
  • Memory control logic
  • Handle N incoming and outgoing packets in ea.
    time slot
  • Memory bandwidth at least the sum of the input
    and output bandwidths
  • Cycle Time cell length (b) / 2 N link speed
    (b/s)

31
Linked-List-Based Shared Memory Switch
32
Hybrid Shared Dedicated Output Buffer Switch
33
Time Division - Shared Medium
34
Advantages/Disadvantages
  • Output modularity
  • Easy implementation
  • Larger buffer requirement for a particular cell
    loss rate
  • Speed has to be N times faster than input ports
  • Input buffering (bus speed has to NxV)

35
Combination - Fully Interconnected
36
Advantages/Disadvantages
  • Queueing at output ports
  • output buffering is desirable (performance point
    of view)
  • hardware requirements on this method are much
    larger than on input buffering
  • Natural multicasting and broadcasting
  • Address filters and buffers
  • simple to implement (not aggregating) and modular
  • speed port speed
  • Scalable to any size and speed
  • Buffer growth is a limiting factor
  • Example Knockout switch

37
  • THE END!

38
Questions Answers
  • Hold your fire!

39
BIBLIOGRAPHY
1 Raed Y. Awdeh and H.T. Mofutah, Survey of
ATM Switch Architectures, Computer Networks and
ISDN Systems, 1995. 2 Fouad A. Tobagi, Fast
Packet Switch Architectures for Broadband
Integrated Services Digital Network, Proceedings
of the IEEE, Jan 1990. 3 Joan Garcia-Haro and
Andrzej Jajszczyk, ATM Shared-Memory Switching
Architectures, IEEE Network, July/Aug 1994. 4
Sanjeev Kumar and Dharma P. Agrawal, On
Multicast Support for Shared-Memory Based ATM
Switch Architecture, IEEE Network, Jan/Feb
1996. 5 Sonia Fahny, A Survey of ATM
Switching Techniques, Department of Computer and
Information Science, The Ohio State University.
http//www.cs.purdue.edu/homes/fahmy/cis788.08Q/at
mswitch.htmlintroAsdf 6 Andrew S. Tanenbaum,
Computer Networks. New Jersey, Prentice Hall
PTR, 1996. 7 Carey Williamson, ATM Switch
Architectures, Department of Computer Science,
University of Saskatchewan. http//www.netera.ca/t
raining_res/3.120Switch20Architectures.ppt
40
Bibliography Contd
  • 8 Daniel Sobirk and Johan M. Karlsson, ATM
    Switching Structures A Performance Comparison,
    Department of Communication Systems, Lund
    Institute of Technology. http//www.tts.lth.se/Pe
    rsonal/daniels/papers/nts12.pdf
  • 9 Barry Hill, ATM Asynchronous Transfer
    Mode, Machine Vision Laboratory, Worcester
    Polytechnic Institute. http//www.ece.wpi.edu/cour
    ses/ee535/hwk11cd95/bkh/bisdn.html
  • 10 Gail C. Hudek, Blocking in Digital
    Cross-Connect Systems, IEEE Network, Jan 1993.
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