Ignacio Lpez, Rubn Salvador, Jaime Alarcn, Flix Moreno - PowerPoint PPT Presentation

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Ignacio Lpez, Rubn Salvador, Jaime Alarcn, Flix Moreno

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RoI Extractor detects the RoI. GNN process RoDs 'Probability' detection map obtained ... RoI Extractor RoI Buffer. GNN. KNU. GNN Single layer perceptron 30x3 ... – PowerPoint PPT presentation

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Title: Ignacio Lpez, Rubn Salvador, Jaime Alarcn, Flix Moreno


1
Architectural design for a low cost FPGA-based
traffic signal detection system in vehicles
  • Ignacio López, Rubén Salvador, Jaime Alarcón,
    Félix Moreno
  • ruben.salvador_at_upm.es
  • CEI - Centro de Electrónica Industrial
  • ASLab - Autonomous System Laboratory
  • Universidad Politécnica de Madrid (Spain)

2
Motivation
  • ADAS (Advanced Driver Assistance Systems)
  • Real-time analysis of complex driving scenarios
  • Risk evaluation. Anticipation

3
Motivation
  • Low cost systems
  • Low cost CCD cameras and FPGAs
  • Mass production. Introduction in the market
  • Scarce HW resources
  • Architecture developed for optimal use
  • Blackboard Architecture
  • Neural Networks in reconfigurable HW
  • Real-time classification systems
  • HMI (Human-Machine Interface)

4
Outline
  • System Requirements
  • Reference Architecture
  • Blackboard architecture (BB1/AIS)
  • Neural network topology
  • Implementation architecture
  • Hardware Architecture
  • Features, optimizations, performance
  • Results
  • Conclusions
  • System evolution

5
System Requirements
Scalability
Low cost
Flexibility
FPGA
BB1
Real time
Reconfigurability
Predictability
Integrability
6
Outline
  • System Requirements
  • Reference Architecture
  • Blackboard architecture (BB1/AIS)
  • Neural network topology
  • Implementation architecture
  • Hardware Architecture
  • Features, optimizations, performance
  • Conclusions
  • System evolution

7
Reference Architecture. Blackboard Architecture
  • Simplified BB1/AIS architecture

8
Reference Architecture. Neural network topology
  • Neural networks ?? hugely resource consuming

super-net
atomization
  • Identification of singularities
  • characteristic elements of shape
  • 8x8 pixel region
  • Function specialized networks
  • Collaborative networks
  • Single layer perceptrons
  • Challenge ? Performance/Cost Trade-off
  • Exploit FPGA parallel architecture...
  • ... and its potential for reconfigurability

9
Outline
  • System Requirements
  • Reference Architecture
  • Blackboard architecture (BB1/AIS)
  • Neural network topology
  • Implementation architecture
  • Hardware Architecture
  • Features, optimizations, performance
  • Results
  • Conclusions
  • System evolution

10
Hardware architecture
  • Communications Interface and Preprocessor
  • Minimize the use of large memory banks
  • Minimize the complexity of the control

11
Hardware architecture
  • Knowledge unit (KNU).
  • Preliminary stimations ? impossible to implement
    more than one KNU in a single FPGA
  • Problem overcome
  • Build a single, generic neural network optimized
    in time to be run several times
  • Datapath
  • No overflows - Saturation
  • Fixed point
  • Signed fractional
  • Q10.22 Q25.44

12
Hardware architecture
  • Mode of operation
  • Computational load decrease ? RoI
  • Singularity detection ? RoD
  • 10x9 RoDs per RoI
  • RoI Extractor detects the RoI
  • GNN process RoDs
  • Probability detection map obtained
  • Modularity
  • Distributed layer control
  • Layer modules
  • Implementation on different FPGAs

13
Hardware architecture
Less LEs Fmax increase Scalability
  • Architecture optimizations
  • Binary images ? Thresholding
  • Q8.16 format
  • Design for reuse methodology
  • GNN performance
  • 73 clock cycles

14
Outline
  • System Requirements
  • Reference Architecture
  • Blackboard architecture (BB1/AIS)
  • Neural network topology
  • Implementation architecture
  • Hardware Architecture
  • Features, optimizations, performance
  • Results
  • Conclusions
  • System evolution

15
Results
GNN ? Single layer perceptron 30x3
  • Altera CycloneEP1C20F400C6
  • Altera Cyclone IIEP2C35F672C6

16
Outline
  • System Requirements
  • Reference Architecture
  • Blackboard architecture (BB1/AIS)
  • Neural network topology
  • Implementation architecture
  • Hardware Architecture
  • Features, optimizations, performance
  • Results
  • Conclusions
  • System evolution

17
Conclusions
  • Traffic signal identification in urban areas
  • Low cost
  • Flexibility
  • Scalability
  • Integrability
  • Predictability
  • Reconfigurability
  • Efficient usage of resources

18
Outline
  • System Requirements
  • Reference Architecture
  • Blackboard architecture (BB1/AIS)
  • Neural network topology
  • Implementation architecture
  • Hardware Architecture
  • Features, optimizations, performance
  • Results
  • Conclusions
  • System evolution

19
System evolution
  • Fully develop Blackboard architecture
  • Pedestrian detection
  • System reconsideration
  • GNN distribution
  • FPGA
  • Self adjustable RoI processing strategy
  • Autonomous vehicles - Robots
  • FPGA benchmark
  • Cognitive architectures scalability
  • Hardware embedded intelligence
  • Implementation methodology
  • Features conservation

20
Thank you for your attention!! ruben.salvador_at_upm.
es
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