CMOS VLSI DESIGN CMOS VLSI Tasarim

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CMOS VLSI DESIGNCMOS VLSI Tasarim

• Hafta 4
• Ali Ziya Alkar

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Standard Cell Layout Methodology
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Two Versions of (ab).c
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Logic Graph
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Consistent Euler Path
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Example x abcd
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CMOS kapasiteleri

• Oksid Kapasitesi
• Kapi Sigaç Örtüsme Kapasitesi
• Kapi Akaç Örtüsme Kapasitesi
• Kapi Kanal-Bulk Kapasitesi
• Birlesim Kapasitesi
• Akaçtan Bulka birlesim
• Sigaçtan Bulka birlesim

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Oksid-Örtüsme Kapasiteleri
Ld kapasitesi her iki tarafta da oksidin altinda
kalir Leff L drawn 2Ld Toplam Örtüsme
Kapasitesi
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Oksid-Kanal Kapasitesi

• Kapi-Akaç
• Kapi-Sigaç
• Kapi-Bulk

Cut off durumu
Bu durumda kanal olmadigindan dolayi toplam
kapasite CcCgb dir.
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Oksid Kapasitesi
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Oksid Kapasitesi
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Oksid Kapasiteleri
Cut-off
Resistive
Saturation
Sayisal Tasarimdaki En önemli Bölgeler SAT ve
CUTOFF
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Kapi Kapasiteleri
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Baglanti - Junction Kapasitesi
Kanal-Implant durma noktasi
Yan Duvar
Sigaç
W
N
D
Alt
x
Yan Duvar
j
Kanal
L
Alttas
N
S
A
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Baglanti - Junction Kapasitesi
0 bias voltajindaki bir PN baglantisindaki
kapasite
Genel olarak, m degeri 0.3-0.5 arasi kullanilir.
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Baglanti - Junction Kapasitesi
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Baglanti Kapasitesi
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0.25 mm CMOS süreçte kapasiteler
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Mikron alti - Sub-Micron - MOS Transistor

• Esik Voltaji Degisimleri
• Esikalti Iletim
• Parazitik dirençler

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Esik voltaji Degisimleri
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Esik Voltaji Degisimleri
Low
V

threshold
Long-channel threshold
DS
VDS
L
Threshold as a function of
Drain-induced barrier lowering
the length (for low
V
)
(for low
L
)
DS
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Esik voltaji Degisimleri
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Hot carrier
The drain avalanche hot carrier (DAHC) injection
is said to produce the worst device degradation
under normal operating temperature range. This
occurs when a high voltage applied at the drain
under non-saturated conditions (VDgtVG) results in
very high electric fields near the drain, which
accelerate channel carriers into the drain's
depletion region. Studies have shown that the
worst effects occur when VD 2VG. The
acceleration of the channel carriers causes them
to collide with Si lattice atoms, creating
dislodged electron-hole pairs in the process. 
This phenomenon is known as impact ionization,
with some of the displaced e-h pairs also gaining
enough energy to overcome the electric potential
barrier between the silicon substrate and the
gate oxide.                                
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• Under the influence of drain-to-gate field, hot
  carriers that surmount the substrate-gate oxide
  barrier get injected into the gate oxide layer
  where they are sometimes trapped. This hot
  carrier injection process occurs mainly in a
  narrow injection zone at the drain end of the
  device where the lateral field is at its maximum.
       
• Hot carriers can be trapped at the Si-SiO2
  interface (hence referred to as 'interface
  states') or within the oxide itself, forming a
  space charge (volume charge) that increases over
  time as more charges are trapped. These trapped
  charges shift some of the characteristics of the
  device, such as its threshold voltage (Vth) and
  its conveyed conductance (gm)
• Injected carriers that do not get trapped in the
  gate oxide become gate current. On the other
  hand, majority of the holes from the e-h pairs
  generated by impact ionization flow back to the
  substrate, comprising a large portion of the
  substrate's drift current. Excessive substrate
  current may therefore be an indication of hot
  carrier degradation.  In gross cases, abnormally
  high substrate current can upset the balance of
  carrier flow and facilitate latch-up.

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• Channel hot electron (CHE) injection occurs when
  both the gate voltage and the drain voltage are
  significantly higher than the source voltage,
  with VGVD.  Channel carriers that travel from
  the source to the drain are sometimes driven
  towards the gate oxide even before they reach the
  drain because of the high gate voltage.     

                      Figure 2.  CHE injection
involves propelling of carriers in the channel
toward the oxide even before they reach the drain
area source Hitachi Semiconductor Reliability
Handbook
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• Substrate hot electron (SHE) injection occurs
  when the substrate back bias is very positive or
  very negative, i.e.,  VBgtgt 0. Under this
  condition, carriers of one type in the substrate
  are driven by the substrate field toward the
  Si-SiO2 interface. As they move toward the
  substrate-oxide interface, they further gain
  kinetic energy from the high field in surface
  depletion region.  They eventually overcome the
  surface energy barrier and get injected into the
  gate oxide, where some of them are trapped.
•           

                        Figure 3.  SHE injection
involves trapping of carriers from the
substrate source Hitachi Semiconductor
Reliability Handbook 
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Esik alti iletim
Vgs lt Vt için de iletim olmaktadir!Esik alti
kaçak akimi akmaktadir.
Egim Faktörü
S DVGS ID2/ID1 10 durumunda
S degeri tipik olarak 60 .. 100 mV
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Esik alti ID vs VGS
VDS from 0 to 0.5V
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Esik altiID vs VDS
VGS from 0 to 0.3V
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Parazitik Dirençler
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Kaçak Akim

• Kaçak akimin etkileri
• Stand by durumunda bosa harcanan güç
• Kaçak akim isinin artmasina neden olur
• Dogru ve güvenilirlikten uzaklasma
• Çözüm
• Uzun kanal
• Düsük Vds voltajlari
• Yüksek Vt

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Kaçak Akim

• Trade off durumu
• Yüksek hiz için düsük Vt ve L degerleri gerekir
• Düsük kaçak için yüksek Vt ve L degeri gerekir.
• Yeniden boyutlandirma
• Lyi ve Vtyi düsürür
• Ancak her YB x10 kaçagi artirir.
• Sonuç
• Yüksek Vtli transistörleri güç tasarruf
  durumunda
• Düsük Vtlileri hiz gerektiren kritik yollarda
  kullan

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Latch-up

• An SCR is a 3-terminal 4-layered p-n-p-n device
  that basically consists of a PNP transistor and
  an NPN transistor as shown in Figure on right. An
  SCR is 'off' during its normal state but will
  conduct current in one direction (from anode to
  cathode) once triggered at its gate, and will do
  so continuously as long as the current through it
  stays above a 'holding' level.  This is easily
  seen in Figure 1, which shows that 'triggering'
  the emitter of T1 into conduction would inject
  current into the base of T2.  This would drive T2
  into conduction, which would forward bias the
  emitter-base junction of T1 further, causing T1
  to feed more current into the base of T2.  Thus,
  T1 and T2 would feed each other with currents
  that would keep both of them saturated

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• Kuyuya veya alttasa gelen akim BJTleri
  biaslayabilir.
• Birinin ON olmasi positif geribesleme sonucu VDD
  ve GNDu birlestirir.
• Çözüm Devredeki dirençleri düsürmek. Alttas
  Taplari (Substrate Tap) koymak
• Veya yüksek akimalarda koruma çemberi (Guard
  Ring) önerilir.

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Latch up
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MOS SPICE PARAMETRELERI
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Parazitik SPICE Parametreleri
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SPICE Transistor Parametreleri
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Hatlar
sematik
fiziksel
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BaglantininYonga Üstünde Etkisi
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Hat Modelleri
Capacitance-only
All-inclusive model
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Baglantin Parazitik Etkisi

• Interconnect parasitics
• reduce reliability
• affect performance and power consumption
• Classes of parasitics
• Capacitive
• Resistive
• Inductive

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Baglantinin Dogasi
Global Interconnect
Source Intel
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Baglanti
Kapasite
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Baglanti Kapasitesi
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Kapasite Parallel Plaka Modeli
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Permitivite
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Hat kapasitesi (0.25 mm CMOS)
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Wire Capacitance

• Wire has capacitance per unit length
• To neighbors
• To layers above and below
• Ctotal Ctop Cbot 2Cadj

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Capacitance Trends

• Parallel plate equation C eA/d
• Wires are not parallel plates, but obey trends
• Increasing area (W, t) increases capacitance
• Increasing distance (s, h) decreases capacitance
• Dielectric constant
• e ke0
• e0 8.85 x 10-14 F/cm
• k 3.9 for SiO2
• Processes are starting to use low-k dielectrics
• k ? 3 (or less) as dielectrics use air pockets

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M2 Capacitance Data

• Typical wires have 0.2 fF/mm
• Compare to 2 fF/mm for gate capacitance

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Diffusion Polysilicon

• Diffusion capacitance is very high (about 2
  fF/mm)
• Comparable to gate capacitance
• Diffusion also has high resistance
• Avoid using diffusion runners for wires!
• Polysilicon has lower C but high R
• Use for transistor gates
• Occasionally for very short wires between gates

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Standard Unite Kapasitesi
Her teknoloji alani için ayri ayri
hesaplanabilir. Önceki tablo kullanilir. Örnegin
5µ proses için A25 µm2 oldugundan ?Cg degeri
25 µm x 4 x 10-4 0.01 pf
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Standard Unite Kapasitesi
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Baglanti
Direnç
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Hat Direnci
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Hat Geometrisi

• Pitch w s
• Aspect ratio AR t/w
• Old processes had AR ltlt 1
• Modern processes have AR ? 2
• Pack in many skinny wires

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Katmanlar

• AMI 0.6 mm process has 3 metal layers
• Modern processes use 6-10 metal layers
• Example
• Intel 180 nm process
• M1 thin, narrow (lt 3l)
• High density cells
• M2-M4 thicker
• For longer wires
• M5-M6 thickest
• For VDD, GND, clk

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Hat Direnci

• r resistivity (Wm)

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Hat Direnci

• r resistivity (Wm)

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Hat Direnci

• r resistivity (Wm)
• R? sheet resistance (W/?)
• ? is a dimensionless unit(!)
• Count number of squares
• R R? ( of squares)

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Metal Seçimi

• Until 180 nm generation, most wires were aluminum
• Modern processes often use copper
• Cu atoms diffuse into silicon and damage FETs
• Must be surrounded by a diffusion barrier

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Sheet Resistance

• Typical sheet resistances in 180 nm process

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Direnç

• Selective Technology Scaling
• Use Better Interconnect Materials
• reduce average wire-length
• e.g. copper, silicides
• More Interconnect Layers
• reduce average wire-length

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Polycide Gate MOSFET
Silicide
PolySilicon
SiO
2


n
n
p
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Modern Baglantilar
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Contacts Resistance

• Contacts and vias also have 2-20 W
• Use many contacts for lower R
• Many small contacts for current crowding around
  periphery

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Örnek Intel 0.25 micron Süreç
5 metal layers Ti/Al - Cu/Ti/TiN Polysilicon
dielectric
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Lumped Model
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Oneriler
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