COMBINATIONAL LOGIC

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COMBINATIONAL LOGIC
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Overview
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Combinational vs. Sequential Logic
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Static CMOS Circuit
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Static CMOS
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NMOS Transistors in Series/Parallel Connection
Transistors can be thought as a switch controlled
by its gate signal NMOS switch closes when switch
control input is high
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PMOS Transistors in Series/Parallel Connection
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Complementary CMOS Logic Style Construction
(cont.)
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Example Gate NAND
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Example Gate NOR
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Example Gate COMPLEX CMOS GATE
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4-input NAND Gate
Vdd
Out
GND
In1
In2
In3
In4
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Standard Cell Layout Methodology
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Two Versions of (ab).c
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Logic Graph
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Consistent Euler Path
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Example x abcd
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Properties of Complementary CMOS Gates
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Properties of Complementary CMOS Gates
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Transistor Sizing
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Propagation Delay Analysis - The Switch Model
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What is the Value of Ron?
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Numerical Examples of Resistances for 1.2mm CMOS
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Analysis of Propagation Delay
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Design for Worst Case
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Influence of Fan-In and Fan-Out on Delay
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tp as a function of Fan-In
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Fast Complex Gate - Design Techniques
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Fast Complex Gate - Design Techniques (2)
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Fast Complex Gate - Design Techniques (3)
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Fast Complex Gate - Design Techniques (4)
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Example Full Adder
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A Revised Adder Circuit