XpressFlow 2080

1

• XpressFlow 2080
• DS213/2
• DS113/2

2
XF 2080 Family Overview

• Total family consists of Two Groups
• L2 Chip Sets Perfect for 241 242 system
• DS112 and DS113 for Unmanaged L2 Applications
• DS212 and DS213 for Managed L2 Applications
• L2/L3/L4 Chip Sets
• Target L3/L4 241, 242 and L2/L3/L4 stackable
  system
• DS312, DS313, DS342 for L3/L4 Applications
• SF240 for use with the DS3xx devices
• All Chips Support Full wire-speed
• Leading edge features and capabilities

3
Target Marketfor DS213/2 DS113/2
First 2-chip Solution for 242 and 241
Configuration
managed
unmanaged
workgroup
enterprise
wiring closet
desktop
4
Market Trends

• Gigabit Ready
• GB PHY for Copper Available
• Uplink for Switch Interconnection or Servers
• New QoS requirements
• Traffic Classification for VoIP vs. Data stream
• Cost and Performance
• Cost effective 2 Chip Solution for 242G
• System must support Full wire-speed

5
Key Benefits

• First Chip on Market with 12x10/100 1G
• Time to Market for 242, 241 and 121 System
• System Ready Including
• Chip Sets
• Software and Microcode
• Reference Designs
• Layout, BOM
• Manuals
• Very Cost Effective
• First 2-chip Solution for 242 Full Wire-Speed
• Compare with existing solution at least 6 Chips.

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XpressFlow 2080Managed Switch Engines

• Target applications
• 12x10/100 switch
• 12x10/100 1 Gig switch
• 24x10/100 switch
• 24x10/100 1 Gig switch
• 24x10/100 2 Gig switch
• Managed intelligent switches
• Full wirespeed packet forwarding
• Provides IP Multicast by IGMP snooping
• 2k MAC addresses on Chip
• 16K MAC addresses on SRAM using Mirocode
• Port trunking - 4 groups, max of 8 ports per group

• Fast Ethernet
• Distributed Switch
• 12 10/100 ports 1
• Gigabit Ethernet Uplink
• 6.4Gb/s connection to
• another DS213 or DS212
• 3.27Mpps forwarding rate
• Layer 2 switching only

DS213

• Fast Ethernet
• Distributed Switch
• 12 10/100 ports
• 6.4Gb/s connection to
• another DS212 or DS213
• 1.78Mpps forwarding rate
• Layer 2 switching only

DS212
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XpressFlow 2080Unmanaged Switch Engines

• Target applications
• Unmanaged Switches with the following port
  configurations
• 12x10/100 switch (Gigabit Ready)
• 12x10/100 1 Gig switch
• 24x10/100 switch
• 24x10/100 1 Gig switch
• 24x10/100 2 Gig switch
• Full wirespeed packet forwarding in 1 or 2 chip
  configurations
• 2k MAC addresses internal to each chip
• Efficient LED interface
• Parallel EEPROM for power-on configuration

• Fast Ethernet
• Distributed Switch
• 12 10/100 ports 1
• Gigabit Ethernet Uplink
• 6.4Gb/s connection to
• another DS113 or DS112
• 3.27Mpps forwarding rate
• Layer 2 switching only

DS113

• Fast Ethernet
• Distributed Switch
• 12 10/100 ports
• 6.4Gb/s connection to
• another DS112 or DS113
• 1.78Mpps forwarding rate
• Layer 2 switching only

DS112
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DS212/3 Overview
XpressFlow Pipe
32 _at_ 100Mhz
32 _at_ 100Mhz
Management, EPROM xface
DS212 12-Port 10/100Mb/s Distributed Switch
32
SBRAM 0.5 - 2 MB
64 _at_100Mhz
Packet Buffer Memory
1 GBE Port (DS213) GMII/TBI(PCS)
12 FE Ports RMII
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Block DiagramDS213
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DS213/2 Features

• Low latency thru single store-and-forward
• Packets buffered at ingress, until output port is
  ready
• Latency 3-8us typ. (last bit in to first bit
  out)
• On-chip address resolution of Layer 2 packets
• Up to 2k MAC addresses on chip
• Up to 16k MAC addresses using on Chip Microcode
• Address self-learning, aging and replacement
• Packets transferred between chips in granules
  (0-128B)
• Reduces messaging overhead (granule header
  between 4-8bytes)
• Allows multiple streams to be multiplexed through
  system

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DS213/2 Features

• Port and ID tagged VLANs (802.1Q)
• Up to 256 VLANs
• Tag insertion/extraction
• Multiple VLANs per MAC
• Multiple VLANs per Port
• Class of Service (802.1p)
• 4 queues per output port
• Queue priority based upon VLAN ID tag
• Transmission scheduled using Weighted Round Robin
  (WRR)
• User defined mapping of priority levels and
  weights
• HOLB Prevention

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DS213/2 Features

• Packet filtering
• Static MAC address filtering - src dest
• Protocol filtering
• Blocking of 8 types of packets (pkt
  encapsulation)
• User selectable for each chip
• Port security
• Limit number of MAC addresses learned/port
• Static MAC addresses can have aging turned off

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DS213/2 Features

• Port trunking and load sharing
• 4 groups total, max of 8 ports per group
• Trunked ports must reside in same chip VLAN
• Load sharing based upon source destination MAC
  addresses
• Broadcast and flooding control
• user programmable limit to broadcast/flooded
  traffic
• Full-duplex flow control (802.3x)
• Backpressure for half-duplex

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DS213/2 Features

• IP Multicast support through IGMP snooping
• IGMP packets passed to management CPU for setup
  and tear down of IP Multicast Group Membership
• IP Multicast Groups utilize VLAN multicast tables
• Maximum of 256 VLAN and IP Multicast Groups
• Port Mirroring provided through dedicated port or
  Port 0 (of the 12/24 output ports)
• Gigabit Ethernet ports can not be mirrored

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DS213/2 Features

• XpressFlow Pipe interface
• 32-bit, 100Mhz gt 3.2Gb/s
• Separate transmit and receive ports
• Data buffer memory bandwidth of 6.4Gb/s
• Separate Management CPU interface

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12-Port 10/100 w/ Gigabit Uplink Applications
Unmanaged
Managed
Management CPU
EPROM
EPROM
DS113 121 Distributed Switch
DS213 121 Distributed Switch
Buffer Memory
Buffer Memory
12 Fast Ethernet Ports
Gigabit Ethernet Port
12 Fast Ethernet Ports
Gigabit Ethernet Port
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Unmanaged 24 1 Application
EPROM
DS112 12 Port Distributed Switch
DS113 121 Distributed Switch
Buffer Memory
Buffer Memory
12 Fast Ethernet Ports
12 Fast Ethernet Ports
Gigabit Ethernet Port
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Managed 24 2 Application
Switch Manager CPU
Local Control Console
Management Bus
DS213 121 Distributed Switch
DS213 121 Distributed Switch
Buffer Memory
Buffer Memory
12 Fast Ethernet Ports
Gigabit Ethernet Port
12 Fast Ethernet Ports
Gigabit Ethernet Port
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Software Components

• Primary Software
• Real-Time Multitasking Kernel (Nucleus)
• System Drivers
• Boot Code
• Debug Monitor
• Basic Diagnostics
• Microcode for Distributed Engines
• DS212/DS213
• DS112/DS113
• Network Protocols
• 802.1D Bridging
• Spanning Tree Protocol
• Port ID tagging VLAN (IEEE 802.1Q), IP
  Multicast (IGMP), QoS/CoS (IEEE 802.1p/Q)
• GARP/GVRP

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Software Components

• Management Functions
• Three console interface options
• Local Management Console
• Remote Management Console (Telnet)
• Web-based browser console interface
• SNMP Agent and MIB-II
• RMON agent and MIB (RFC 1757)
• Hardware counters for statistics
• Bridge MIB (RFC 1286)
• Remote Software Upgrade (TFTP)

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Competitive Matrix
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Key Benefits

• First Chip on Market with 12x10/100 1G
• Support for high-speed Gigabit Ethernet uplinks
• L2 Full Wire-Speed
• Powerful Qos/CoS capabilities
• Very cost effective
• Single Chip Solution for 12 1 system (compare
  3 Chips),
• 2 Chips Solution for 241 and 24 2 system
  (compare 6 chips)
• Fast Time to Market with System Ready Reference
  Designs
• Total system Solution and Ready to Ship
• Complete H/W and S/W components

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Key Benefits

• Common architecture for broad range of LAN/WAN
  switching products
• Scalable Flexible architecture
• Timely upgrades with firmware
• Engines based on programmable HISC CPU cores
• Ability to modify headers for WAN applications

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Vertex Networks Solutions

• Customer designs switch system
• Vertex provides
• Reference designs, manuals, layout, BOM
• Chipsets and software
• Benefits
• Complete control of design process
• Customized for end-user application