Combinational Logic Circuits read Chapter 2 in Mano

1
Combinational Logic Circuits(read Chapter 2 in
Mano)

• Binary Logic and Gates
• Logic Simulation
• Boolean Algebra
• Standard Forms
• Karnaugh Maps
• NAND/NOR and XOR gates

2
Schematic for 4 Bit ALU
Invertor
ANDGate
EXORGate
ORGate
3
Simulation of 4 Bit ALU

• if S0 then DB-A
• if S1 then DA-B
• if S2 then DAB
• if S3 then D-A

4
Elementary Binary Logic Functions

• Digital circuits represent information using two
  voltage levels.
• binary variables are used to denote these values
• by convention, the values are called 1 and 0
  and we often think of them as meaning True and
  False
• Functions of binary variables are called logic
  functions.
• AND(A,B) 1 if A1 and B1, else it is zero.
• AND is generally written in the shorthand AB (or
  AB or AÙB)
• OR(A,B) 1 if A1 or B1, else it is zero.
• OR is generally written in the shorthand form AB
  (or AB or AÚB)
• NOT(A) 1 if A0 else it is zero.
• NOT is generally written in the shorthand form
  (or ØA or A?)

• AND, OR and NOT can be used to express all other
  logic functions.

5
Two Variable Binary Logic Functions

• Can make similar truth tables for 3 variable or 4
  variable functions, but gets big (256 65,536
  columns).

• Representing functions in terms of AND, OR, NOT.
• NAND(A,B) (AB)?
• EXOR(A,B) (A?B) (AB ?)

6
Basic Logic Gates

• Logic gates compute elementary binary
  functions.
• output of an AND gate is 1 when both of its
  inputs are 1, otherwise the output is zero
• similarly for OR gate and inverter

• Timing diagram shows how output values change
  over time as input values change.

7
Multivariable Gates
6 input OR Gate
3 input AND Gate
ABCDEF
ABC

• AND function on n variables is 1 if and only
  if ALL its arguments are 1.
• n input AND gate output is 1 if all inputs are
  1
• OR function on n variables is 1 if and only if
  at least one of its arguments is 1.
• n input OR gate output is 1 if any inputs are
  1
• Can construct large gates from 2 input gates.
• however, large gates can be less expensive than
  required number of 2 input gates

8
Elements of Boolean Algebra

• Boolean algebra defines rules for manipulating
  symbolic binary logic expressions.
• a symbolic binary logic expression consists of
  binary variables and the operators AND, OR and
  NOT (e.g. ABC?)
• The possible values for any Boolean expression
  can be tabulated in a truth table.

• Can define circuit forexpression by
  combininggates.

9
Schematic Capture Logic Simulation
wires
advancesimulation
gates
signalwaveforms
terminals
schematicentry tools
signalnames
10
Tool Installation

• Tools can be installed automatically from CD-ROM.
• full installation requires about 700 MB of disk
  space
• required components are design entry,
  simulation, help viewer - not implementation
• you will need Serial and CD Key from card in
  package with CD
• Obtain license file from Cadence Web site.
• go to http//www.xilinx.com/univ/ and click on
  Student Edition Software link and then Student
  Edition License Generator link
• follow instructions to register and generate the
  license file
• you need serial (on slip of paper with CDROM),
  CD Key and either Ethernet address (type
  c\fndtn\bin\nt\lmutil lmhostid -ether in DOS
  window - modify if software in non-default
  location) or C drive serial number (type vol c
  in DOS window)
• license file appears in text window
• copy all text from browser to Notepad (using
  copy/paste) and save in file C\fndtn\data\license
  .dat (modify if software in non-default location)
• in DOS window, type setmore and look for line
  assigning value to LM_LICENSE_FILE make sure it
  points to location of license.dat
• if not, edit C\Autoexec.bat using Notepad to
  include line containingSET LM_LICENSE_FILEC\fnd
  tn\data\license.dat and REBOOT
• type type LM_LICENSE_FILE in DOS window to
  verify file contents

11
License Generation (1)
www.xilinx.com/univ/
link toStudent Editionsoftware
12
License Generation (2)
www.xilinx.com/univ/xse1.htm
link to LicenseGenerator
13
License Generation (3)
www.xilinx.com/univ/xsepre.htm
registerfirst
then generatelicense
14
License Generation (4)
fill inblanks
15
License Generation (5)
serial numberfrom package
host id C drivevolume
last steppress button
16
Starting New Project

• Start Project Manager by selecting
• Start ?
• Programs ?
• Xilinx Foundation Series ?
• Xilinx Foundation Project Manager

selectschematicentry
enter name
selectnew project
selectschematic
selectSpartan
17
Defining Circuit
startsimulator
symbolstoolbox
wiringtool
defineterminals
entername
2 inputAND
selecttype
18
Simulate Circuit
6. click on Stepbutton to advancesimulation
1. select addsignals
3. click onstimulatorbutton
2. select signalsand Add
5. click oncounter bits
4. select signalsand ...
19
Boolean Functions to Logic Circuits

• Any Boolean expression can be converted to a
  logic circuit made up of AND, OR and NOT gates.
• step 1 add parentheses to expression to fully
  define order of operations - A(B(C ?))
• step 2 create gate for last operation in
  expression
• gates output is value of expression
• gates inputs are expressions combined by
  operation

• step 3 repeat for sub-expressions and continue
  until done
• Number of simple gates needed to implement
  expression equals number of operations in
  expression.
• so, simpler equivalent expression yields less
  expensive circuit
• Boolean algebra provides rules for simplifying
  expressions

20
Basic Identities of Boolean Algebra

• 1. X 0 X
• 3. X 1 1
• 5. X X X
• 7. X X 1
• 9. (X ) X
• 10. X Y Y X
• 12. X(YZ ) (XY )Z
• 14. X(YZ ) XY XZ
• 16. (X Y )? X ?Y ?

2. X1 X 4. X0 0 6. XX X 8. XX
0 11. XY YX 13. X(YZ ) (XY
)Z 15. X(YZ ) (XY )(XZ ) 17. (XY) X
?Y ?
commutative associative distributive DeMorgans

• Identities define intrinsic properties of Boolean
  algebra.
• Useful in simplifying Boolean expressions
• Note 15-17 have no counterpart in ordinary
  algebra.
• Parallel columns illustrate duality principle.

21
Verifying Identities Using Truth Tables

• Can verify any logical equation with small number
  of variables using truth tables.
• Break large expressions into parts, as needed.

22
DeMorgans Laws for n Variables

• We can extend DeMorgans laws to 3 variables by
  applying the laws for two variables.
• (X Y Z )? (X (Y Z ))? - by associative
  law
• X ?(Y Z )? - by DeMorgans law
• X ?(Y ?Z ?) - by DeMorgans law
• X ?Y ?Z ? - by associative law
• (XYZ)? (X(YZ ))? - by associative law
• X ? (YZ )? - by DeMorgans law
• X ? (Y ? Z ?) - by DeMorgans law
• X ? Y ? Z ? - by associative law
• Generalization to n variables.
• (X1 X2 Xn)? X ?1X ?2 X ?n
• (X1X2 Xn)? X ?1 X ?2 X ?n

23
Simplification of Boolean Expressions
FX ?YZ X ?YZ ?XZ
24
The Duality Principle

• The dual of a Boolean expression is obtained by
  interchanging all ANDs and ORs, and all 0s and
  1s.
• example the dual of A(BC ?)0 is A(BC ?)1
• The duality principle states that if E1 and E2
  are Boolean expressions then
• E1 E2 ? dual (E1)dual (E2)
• where dual(E) is the dual of E. For example,
• A(BC ?)0 (B ?C )D ? A(BC ?)1 (B
  ?C )D
• Consequently, the pairs of identities (1,2),
  (3,4), (5,6), (7,8), (10,11), (12,13), (14,15)
  and (16,17) all follow from each other through
  the duality principle.

25
The Consensus Theorem

• Theorem. XY X ?Z YZ XY X ?Z
• Proof. XY X ?Z YZ XY X ?Z YZ(X X ?)
  2,7
• XY X ?Z XYZ X ?YZ 14
• XY XYZ X ?Z X ?YZ 10
• XY(1 Z ) X ?Z(1 Y ) 2,14
• XY X ?Z
  3,2
• Example. (A B )(A? C ) AA? AC A?B BC
• AC A?B BC
• AC A?B
• Dual. (X Y )(X ? Z )(Y Z ) (X Y )(X ?
  Z )

26
Taking the Complement of a Function

• Method 1. Apply DeMorgans Theorem repeatedly.
• (X(Y ?Z ? YZ ))? X ? (Y ?Z ? YZ )?
• X ? (Y ?Z ?)?(YZ )?
• X ? (Y Z )(Y ? Z ?)
• Method 2. Complement literals and take dual
• (X (Y ?Z ? YZ ))? dual (X ?(YZ Y ?Z ?))
• X ? (Y Z )(Y ? Z ?)

27
Sum of Products Form

• The sum of products is one of two standard forms
  for Boolean expressions.
• ?sum-of-products-expression? ?term? ?term?
  ... ?term?
• ?term? ?literal? ?literal?
  ?literal?
• Example. X ?Y ?Z X ?Z XY XYZ
• A minterm is a term that contains every variable,
  in either complemented or uncomplemented form.
• Example. in expression above, X ?Y ?Z is minterm,
  but X ?Z is not
• A sum of minterms expression is a sum of products
  expression in which every term is a minterm.
• Example. X ?Y ?Z X ?YZ XYZ ? XYZ is sum of
  minterms expression that is equivalent to
  expression above.
• Shorthand List minterms numerically. e.g. Sm
  (1,3,6,7)

28
Simplifying Sum-of-Products Expressions

• Sum of products forms yield 2 level AND-OR
  circuits.
• Any expression can be put into sum of products
  form by applying distributive laws.
• The simplest sum of products expression yields
  simplest 2 level AND-OR circuit.
• Any Boolean expression can be viewed as a set of
  minterms.
• An expression F covers another expression G, if
  the minterms in G are a subset of the minterms in
  F.
• AC covers ABC, since AC contains minterms 5 and
  7 (from the set of 8 minterms on the variables A,
  B, and C ) and ABC contains only the minterm 5.

29
General Simplification Procedure

• Given a Boolean expression F.
• Step 1. Let M be the set of minterms covered by
  F.
• Step 2. For each minterm, m, find all terms that
  cover m and also cover other minterms in M,
  but no minterms that are not in M. Let T be
  the resulting set of terms.
• Step 3. Select all terms in T that cover
  minterms covered by no other terms in T.
• Step 4. Select additional terms in T until
  selected terms cover all minterms. At each
  step, select a term that covers the largest
  possible number of new minterms.

30
Example of Simplification

• Let F ABC AB ?D B ?C BCD ? BC ?D ?.
• Step 1. M ABCD,ABCD ?,AB ?CD,AB ?C ?D,AB ?CD
  ?, A?B ?CD,A?B ?CD ?,A?BCD ?,ABC ?D ?,A?BC ?D
  ? or equivalently Sm(15,14,11,9,10,3,2,6,12,4
  )
• Step 2. T AC, AB ?D, B ?C, CD ?, BD ?
• Step 3. Selected terms are AC, AB ?D, B ?C, BD ?
• Step 4. In this case, no additional terms are
  needed to cover all the minterms.
• Result F AC AB ?D B ?C BD ?

31
Karnaugh Maps

• A Karnaugh map is a graphical tool for assisting
  in the general simplification procedure.
• Two variable maps.

FAB A?B AB ?
FAB

• Three variable maps.

FAB ?C ?B ?C ABC BC ?
FAB ?C BC ?
32
Karnaugh Maps

• Four variable maps.

CD
00
01
11
10
AB
FA?BC ?A?CD ?ABC AB ?C?D
?ABC ?AB ?C
0
0
0
1
00
1
1
0
1
01
FBC ?CD ? AC AD ?
1
1
1
1
11
1
0
1
1
10

• Covering 0s gives complement of function.

F ? A?B ?C ?B ?C ?D A?CD F (AB C )(B C D
?)(AC ?D ?)
This gives product of sums form.
33
Dont Care Conditions

• In some situations, we dont care about the value
  of a function for certain combinations of the
  variables.
• these combinations may be impossible in certain
  contexts
• or the value of the function may not matter in
  when the combinations occur
• In such situations we say the function is
  incompletely specified and there are multiple
  (completely specified) logic functions that can
  be used in the design.
• so we can select a function that gives the
  simplest circuit
• When constructing the terms of T in the
  simplification procedure, we can choose to either
  cover or not cover the dont care conditions.

34
Map Simplification with Dont Cares
FA?C?DBAC

• Alternative covering.

FA?B?C?DABC?BCAC
35
Product of Sums Form

• The product of sums is the second standard form
  for Boolean expressions.
• ?product-of-sums-expression? ?s-term?
  ?s-term? ... ?s-term?
• ?s-term? ?literal? ?literal?
  ?literal?
• Example. (X ?Y ?Z )(X ?Z )(X Y )(X Y Z )
• A maxterm is a sum term that contains every
  variable, in complemented or uncomplemented form.
• Example. in exp. above, X ?Y ?Z is a maxterm,
  but X ?Z is not
• A product of maxterms expression is a product of
  sums expression in which every term is a maxterm.
• Example. (X ?Y ?Z )(X ?YZ )(XYZ ?)(XYZ )
  is product of maxterms expression that is
  equivalent to expression above.
• Shorthand List maxterms numerically. e.g. P
  M(6,4,1,0)

36
NAND and NOR Gates

• In certain technologies (including CMOS), a NAND
  (NOR) gate is simpler faster than an AND (OR)
  gate.
• Consequently circuits are often constructed using
  NANDs and NORs directly, instead of ANDs and ORs.
• Alternative gate representations makes this
  easier.

37
Exclusive Or and Odd Function

• The EXOR function is defined by A?B AB ? A?B.

• The odd function on n variables is 1 when an odd
  number of its variables are 1.
• odd(X,Y,Z ) XY ?Z ? X ?Y Z ? X ?Y ?Z X Y Z
  X ?Y ?Z
• similarly for 4 or more variables
• Parity checking circuits use the odd function to
  provide a simple integrity check to verify
  correctness of data.
• any erroneous single bit change will alter value
  of odd function, allowing detection of the change

38
Integrated Circuits

• Digital logic is implemented using transistors in
  integrated circuits containing many gates.
• small-scale integrated circuits (SSI) contain 10
  gates or less
• medium-scale integrated circuits (MSI) contain
  10-100 gates
• large-scale integrated circuits (LSI) contain up
  to 104 gates
• very large-scale integrated circuits (VLSI)
  contain gt104 gates
• Improvements in manufacturing lead to ever
  smaller transistors allowing more per chip.
• gt107 gates/chip now possible doubles every 18
  months or so
• Variety of logic families.
• TTL - transistor-transistor logic
• CMOS - complementary metal-oxide semiconductor
• ECL - emitter-coupled logic
• GaAs - gallium arsenide

39
CMOS Logic Gates

• CMOS integrated circuits are built around using
  two kinds of Field Effect Transistors (FET),
  n-type p-type.

• the gate (note different meaning) input controls
  whether current can flow between the other two
  terminals or not.

• Logic gates are constructed by combining
  transistors in complementary arrangements.

40
Circuit Delays in CMOS Circuits

• Electronic gates are physical devicesthat take
  time to operate.

• Response to instantaneous change atX is gradual
  decrease in voltage atY and similar gradual
  increase at Z.
• Voltage at Y must drop below logicthreshold
  level to be seen as a 0.
• This effect can be viewed as delay in propagation
  of logic values.
• tPLH denotes low-to-high delay
• tPHL denotes high-to-low delay
• tpd maxtPLH, tPHL
• relative values of tPLH and tPHL depend on
  relative strength of pull-up and pull-down
  transistors in inverters
• values vary with operating temperature and
  manufacturing processes

41
Closer Look at CMOS Circuit Delays

• When X goes high, pull-up of first inverter turns
  off and pull-down turns on.

• Decrease of voltage at Y requires transfer of
  charge from capacitor to ground.
• wires and transistor gates act like capacitors
• time for transfer depends on size of capacitance
  and on resistance of pull-down transistor
• pull-up pull-down transistors can have
  different on-state resistance values
• Use of two parallel inverters between X and Y can
  give faster logic transitions.

42
Positive and Negative Logic

• In positive logic systems, a high voltage is
  associated with a logic 1, and a low voltage with
  a logic 0.
• positive logic is just one of two conventions
  that can be used to associate a logic value with
  a voltage
• sometimes it is more convenient to use the
  opposite convention
• In logic diagrams that use negative logic, a
  polarity indicator is used to indicate the
  correct logical interpretation for a signal.

• Circuits commonly use a combination of positive
  and negative logic.

43
Mixed Logic

• In mixed logic systems, both positive and
  negative logic conventions are used.
• signals that are true-high are designated with
  .H appended, and
• signals that are true-low are designated with
  .L appended.

• Here, F.H is equivalent to F XY ? in
  positive logic.
• One uses mixed logic to simplify writing the
  logic for logical equations.