Chap' 9 Instruction Set Architecture

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Chap. 9 Instruction Set Architecture
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Computer Architecture Concepts

• Instruction format
• Opcode field
• Specify the operation to be performed
• Address field
• Provide either a memory address or an address for
  selecting a processor register
• Mode field
• Specify the way the address field is to be
  interpreted

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Computer Architecture Concepts

• Basic computer operation cycle
• Fetch the instruction from memory into a control
  register
• Decode the instruction
• Locate the operands used by the instruction
• Fetch operands from memory (if necessary)
• Execute the operation in processor registers
• Store the results in the proper place
• Go back to step 1 to fetch the next instruction

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Computer Architecture Concepts

• Register Set
• All registers in the CPU that are accessible to
  the programmer
• Mentioned in assembly lang.
• cf) register file for ?-program, pipeline
  registers
• Ex)
• Processor status register (PSR)
• C, N, V, and Z from ALU
• Stack pointer (SP)

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Operand Addressing

• Fetching operand within instruction
• Implied address vs. explicit address
• The number of explicitly addressed operands per
  instruction
• Three-address instructions
• Two-address instructions
• One-address instructions
• Zero-address instructions

long instructions
Many steps of executions
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Operand Addressing

• Three-address Instructions
• Memory-to-memory architecture
• Ex) X(AB)(CD)
• ADD T1, A, B MT1?MAMB
• ADD T2, C, D MT2?MCMD
• MUL X, T1, T2 MX?MT1MT2
• ADD R1, A, B R1?MAMB
• ADD R2, C, D R2?MCMD
• MUL X, R1, R2 MX?R1R2

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Operand Addressing

• Three-address Instructions
• register-to-register (load/store) architecture
• Allow only one memory address
• load, store instructions
• Ex) X(AB)(CD)
• LD R1,A R1?MA
• LD R2,B R2?MB
• ADD R3,R1,R2 R3?R1R2
• LD R1,C R1?MC
• LD R2,D R2?MD
• ADD R1,R1,R2 R1?R1R2
• MUL R1,R1,R3 R1?R1R3
• ST X,R1 MX?R1

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Operand Addressing

• Two-address Instructions
• Ex) X(AB)(CD)
• MOVE T1, A MT1?MA
• ADD T1,B MT1?MT1MB
• MOVE X,C MX?MC
• ADD X,D MX?MXMD
• MUL X,T1 MX?MXMT1
• If register-memory architecture
• ADD R1,A R1?R1MA

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Operand Addressing

• One-address Instructions
• Single-accumulator architecture
• A special register called accumulator for
  obtaining one of the operands and as the location
  of the result
• Ex) X(AB)(CD)
• LD A ACC?MA
• ADD B ACC?ACCMB
• ST X MX?ACC
• LD C ACC?MC
• ADD D ACC?ACCMD
• MUL X ACC?ACCMX
• ST X MX?ACC

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Operand Addressing

• Zero-address Instructions
• Stack architecture
• Ex) X(AB)(CD)
• PUSH A TOS?MA
• PUSH B TOS?MB
• ADD TOS?TOSTOS-1
• PUSH C TOS?MC
• PUSH D TOS?MD
• ADD TOS?TOSTOS-1
• MUL TOS?TOSTOS-1
• POP X MX?TOS

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Stack architecture

• Processing expressions
• Postfix expression
• reverse Polish notation (RPN)
• Ex) (AB)C(DE) ? A B C D E

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1
2
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Stack architecture

• Program for evaluating A B C D E
• PUSH A
• PUSH B
• ADD
• PUSH C
• MUL
• PUSH D
• PUSH E
• MUL
• ADD

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Addressing Modes

• Implied mode
• Immediate mode
• Register and register-indirect mode
• Direct addressing mode
• Indirect addressing mode
• Relative addressing mode
• Indexed addressing mode
• Base-register mode

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Addressing Modes

• Implied mode
• The operand is specified implicitly in the
  definition of the opcode.
• Immediate mode
• The actual operand is specified in the
  instruction itself.

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Addressing Modes

• Register-indirect mode
• For addressing each of elements in arrays
• Ex)
• ADD (R1), 3 MR1?MR13, R1?R11

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Addressing Modes

• Direct addressing mode

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Addressing Modes

• Indirect addressing mode
• Addr. Field of instruction
• Address at which the effective addr. is stored in
  memory
• If indirect mode,

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Addressing Modes

• Indexed addressing mode
• Effective address
• addr. field of instr. index register (offset)
• Base-register mode
• Effective address
• base register addr. field of instr. (offset)

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Addressing Modes (Summary)
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Instruction Set Architecture

• RISC (Reduced Instruction Set Computer)
  Architectures
• Memory accesses are restricted to load and store
  instruction, and data manipulation instructions
  are register to register.
• Addressing modes are limited in number.
• Instruction formats are all of the same length.
• Instructions perform elementary operations
• CISC (Complex Instruction Set Computer)
  Architectures
• Memory access is directly available to most types
  of instruction.
• Addressing mode are substantial in number.
• Instruction formats are of different lengths.
• Instructions perform both elementary and complex
  operations.

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Instruction Set Architecture

• 3 categories of elementary instructions
• Data transfer instructions
• Data manipulation instructions
• Program control instructions