DeFer: Deferred Decision Making Enabled FixedOutline Floorplanner

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DeFerDeferred Decision Making Enabled
Fixed-Outline Floorplanner
Jackey Z. Yan Chris Chu

• Dept. of Electrical Computer Engineering
• Iowa State University
• Ames, IA 50010

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Fixed-Outline Floorplanning

• Earliest Stage of VLSI Physical Design
• Enabling Hierarchical Design
• Important Part in Physical Synthesis

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State-of-the-art Fixed-Outline Floorplanners
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DeFer Overview

• Non-Stochastic
• Handling Hard and Soft Blocks Efficiently
• Promising Experimental Results

• Main Principle Deferred Decision Making (DDM)
• Main Techniques
• Generalized Slicing Tree
• Enumerative Packing (EP)
• Block Swapping and Mirroring

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Constraints of Ordinary Slicing Tree
V
B
E
D
A
H
H
C
B
A
C
V
D
E

• Block orientation

• Slice line direction (H/V)

• Left-right or top-bottom relative order

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DDM in Shape/Orientation

• Defer the decision for subfloorplan (i.e., block)
  orientation until the end

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DDM in Relative Order

• The relative order (left-right / top-down)
  between subfloorplans does not affect the shape
  curves

H
H
ABV
BAV
A
B
A
B
W
W
Same shape curve

• Decision on subfloorplan relative order will be
  made at the end to minimize HPWL

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DDM in Slice Line Direction

• Two combine operators in ordinary slicing tree

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Floorplans by Generalized Slicing Tree
A
B

• Block orientation

• Slice line direction

• Left-right or top-bottom
• relative order

Deferred Decision Making (DDM)
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10
Shape Curve Operation for
?
H
H
C
WH
C
h
B
A
C
v
W
W
( i ) Addition
( iii ) Merging
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DDM in Structure of Slicing Tree
T1
T2
V
H
E
E
H
C
V
D
B
A
A
B
C
D
D
C
E
A
B
Deferred the decision on the structure of
generalized slicing tree!
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Enumerative Packing (EP)
HOW?
K
SK
E
A
B
F
C
G
D
Find shape curve capturing all slicing
trees (i.e., all slicing floorplans)
Given a set of blocks
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Simple Approach of Enumeration
Too Expensive !!!
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Enumeration by Dynamic Programming

• Example To find shape curve for A, B, C, D
• K1 A, B, C, D
• K2 A,B, A,C, A,D, B,C, B,D,
  C,D
• K3 A,B,C, A,B,D, A,C,D, B,C,D
• K4 A,B,C,D

redundant
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Comparison on of Operations
Dynamic Programming (DP) based approach can
significantly reduce runtime and memory.
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Impact of EP on Packing

• Concerns of EP
• Memory and runtime when K is large
• EP considers packing only and ignores wirelength
• A practical approach
• Recursive partitioning until each sub-circuit has
  only a few blocks
• Apply EP to the small sub-circuits

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Flow of DeFer
1. Partitioning
2. Combining
Making Decisions on

• Subfloorplan Orientation

3. Back-Tracing

• Slice Line Direction

• Slicing Tree Structure

4. Swapping

• Subfloorplan Relative Order

5. Compacting
Not restricted to slicing floorplan
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1. Partitioning Step

• Recursively bi-partitioning
• Generate smaller subcircuits
• Minimize interconnections among subcircuits
• Generate high-level slicing tree structure
• Until of blocks in each subcircuits maxN
• (maxN 10 by default)?

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2. Combining Step
100
55
45
35
20
23
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Bottom-up

• Apply EP

5
8
7
9
10
9
19
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3. Back-Tracing Step
Pick one candidate
H
Fixed- outline region
Top-down
W
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4. Swapping Step

• Try to switch two subfloorplans (blocks) to
  improve WL

• Flow
• Rough Swapping
• Detailed Swapping
• Mirroring

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Swapping and Mirroring
Swapping
Mirroring
E
F
E
F
axis
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5. Compacting Step

• Compact towards
• the center
• Improve WL
• Not restricted to
• slicing floorplan

Before
After
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Experiments Setup

• All experiments run on a Linux machine withIntel
  Core Duo 1.86 GHz CPU and 2 GB memory
• GSRC Benchmarks
• Version with hard blocks only
• blocks 100 300
• HB Benchmarks (derived from ISPD 98 benchmarks)
• Mixture of hard and soft blocks (most hard blocks
  are square)
• blocks 500 2000
• 3 different aspect ratios for fixed-outline
  region 1, 2, 3
• Maximum white space 10
• For each test case, average over 100 runs is
  reported

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Result Summary (Normalized)

• GSRC Benchmarks

• HB Benchmarks

1 Saurabh N. Adya and Igor L. Markov. ICCD
2001 2 Tung-Chieh Chen, Yao-Wen Chang and
Shyh-Chang Lin. ICCAD 2005 3 Song Chen and
Takeshi Yosihmura. ISPD 2007 4 Jason Cong,
Michail Romesis and Joseph R. Shinnerl. ASP-DAC
2005
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Conclusions

• DeFer high-quality, fast, robust and
  non-stochastic fixed-outline floorplanner
• Principle of Deferred Decision Making (DDM)
• Generalized Slicing Tree
• Enumerative Packing (EP)
• Block Swapping and Mirroring

• Promising Experimental Results

Best HPWL
All Academic Fixed-outline Floorplanners

• Benchmarks
• GSRC
• HB

V.S.
Best Runtime
Best Success Rate
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Future Work

• Several techniques can be used to further improve
  the quality
• Terminal Propagation
• Greedy Shifting
• DeFer can be applied in other research
• Mixed-size Placement
• Analog Placement with Various Geometry
  Constraints
• Area Minimized Floorplanning
• Floorplanner Integrated SoC Synthesis
• Binary and source code of DeFer will be posted
  online soon http//www.public.iastate.edu/zijuny
  an/

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Thank you!