COMPUTER ORGANISATION

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COMPUTER ORGANISATION (CS - 46)
Sri. RAVISH ARADHYA H. V., Assistant
Professor, R.V.C.E., Bangalore-560 059. e-mail
ravish_aradhya_rvce_at_yahoo.co.in
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Chapter-5ARITHMETIC CIRCUITS. Fast Adder,
Adder/Subtractor, Multiplier Circuits.
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Design of Fast Adders
Principle Calculate the carries quickly,
without waiting for previous stages and feed
into the adders in parallel.
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Design of Fast Adders
Carry Ci1 XiYi YiCi CiXi XiYi Ci
(Xi Yi) Gi CiPi. (Generate Carry Ci
Propagate Carry)
Carry Ci1 Gi CiPi i.e. Ci (Gi-1
Pi-1Ci-1) Ci-1 (Gi-2 Pi-2Ci-2).
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• Design of Fast Adders
• Ci1 Gi CiPi.

always, except when Xi 1 Yi 1.
But, then Gi 1to make Ci1 1 hence Bit cell
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• Design of Fast Adders
• In general C i1 G i PiG i-1
• PiP i-1 G i-2 Pi P i-1 .P 1G0 Pi P
  i-1 P0G0.
• Ci1-- in 3 Gates delay Si in 4 Gates delay
  irrespective of n. C1 in 3 gates delay,C2 in 3
  gates delay,C3 in 3 gates delay and so on. S0 in
  4 gates delay, S1 in 4 gates delay,
  S2 in 4 gates delay and so
  on.

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Implementing these expressions (for a 4-bit
adder), results in the logic diagram. (IC- 74182)
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• Design of Fast Adders
• Carry Ci1 XiYi YiCi CiXi
• Gi CiPi.
• i.e. Ci (Gi-1 Pi-1Ci-1)
• Ci-1 (Gi-2 Pi-2Ci-2).
• In general C i1 G i PiG i-1 PiP i-1 G i-2
  Pi P i-1
• P 1G0 Pi P i-1 P0G0.

Pi
Ai
Si Pi Ci
Bi
Pi Ci Gi Ci 1
Gi
Ci
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• Design of Fast Adders
• i th stage C i1 G i PiG i-1
• PiP i-1 G i-2 Pi P i-1 P 1G0
• Pi P i-1 P0G0.
• C4 Where G i XiYi Pi
  (Xi Yi)
• or (Xi Yi)

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4 bit carry look ahead Adder
4 bit carry look ahead Adder
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4 bit carry look ahead Adder

• independent of n,
• the n-bit addition process requires only four
  gate delays (against 2n)
• increasing n increases gate fan-in
  requirements (C 4 fan_in 5)
• Longer version adders - cascading

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N - bit carry-look ahead adder
General, expressions for Gi Pi are Gk Pk
where k0 for I 4bit adder k1 for II 4bit
adder. For k0 P0 P3P2P1P0 G0
G3P3G2P3P2P1G0. In general C16
G3P3G2P3P2G2 P3P2P1G0
P3P2P1P0C0
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16 bit carry-look ahead adder
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N - bit carry-look ahead adder
32- bit carry-look ahead adder can be realized
using 8-4bit carry look ahead adder. Fan in
requirement for the last set of AND gates still
remains as 5
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Adder/ Subtractor
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Adder/ Subtractor

• control S 0 -- adder.
• S 1 -- subtractor.
• controlling inputs -- all AL
  operations.

Subtractor
Adder
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Adder/ Subtractor
With s 0, Xi Ai Yi Bi Ci 0 With s 1,
Xi Ai Yi Bi Ci 1 combinational ckt
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Adder/ Sub-tractor

• The design equations (k-map) for an adder or a
  subtractor are as below

Y1
Y0
Xn-1
X1
X0
Cn
Fn
F1
F0
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Binary Multiplier

• Unsigned number multiplication
• two n-bit numbers 2n-bit result
• combinational array may be used
• multiplier bit decides
• whether multiplicand to be
• added to incoming PP
• or shift diagonally

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Binary Multiplier
P7, P6, P5,,P0 product
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Array Multiplier
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Array Multiplier
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4 X 3 Multiplier
Prod 7 bits Need 12 AND gates 2-4bit
adders A2 A1 A0 X B3B2B1B0
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Array Multiplier
Array Multiplier has too much delay. has
too much hard ware less precise control
sequential circuits can be used instructions
can be built
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Sequential Multiplier
a
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Flow Chart
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Shift Add Multiplication
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Binary Multiplier
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Feed backs and Suggestions may kindly be sent
to 1. 2. ravish_aradhya_rvce_at_yahoo.co.in
Thank You